- 30 Aug, 2023 40 commits
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Wenjing Liu authored
Redesign pipe resource interfaces in resource.h file. The new interface design addresses the issue with lack of pipe topology encapsulation and lack of pipe accessors. Reviewed-by:
Jun Lei <jun.lei@amd.com> Acked-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
Wenjing Liu <wenjing.liu@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Wenjing Liu authored
Define two new interfaces to update mpc and odm slice count. Reviewed-by:
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Wenjing Liu authored
[why] We need a new algorithm for acquiring secondary opp heads for ODM combine in dcn32 and a release pipe interface to properly release pipe resources. [how] add two new interfaces in DCN specific resource file. Reviewed-by:
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Wenjing Liu authored
We are renaming acquire first free pipe to add otg master pipe for stream because the former name doesn't indicate that it acquires the first free pipe to use as an otg master pipe. This could cause coding errors if someone uses it to acquire a different pipe type. Reviewed-by:
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Wenjing Liu authored
Adding detail comments describing the problem we are solving with add plane function. Reviewed-by:
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Mustapha Ghaddar authored
For DPIA we should have preferred DIG assignment based on DPIA selected as per the ASIC design. Reviewed-by:
George Shen <george.shen@amd.com> Acked-by:
Mustapha Ghaddar <mghaddar@amd.com> Signed-off-by:
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Wenjing Liu authored
When we are dynamically adding new ODM slices, we didn't update blank state, if the pipe used by new ODM slice is previously blanked, we will continue outputting blank pixel data on that slice causing right half of the screen showing blank image. The previous fix was a temporary hack to directly update current state when committing new state. This could potentially cause hw and sw state synchronization issues and it is not permitted by dc commit design. Cc: stable@vger.kernel.org Fixes: 7fbf451e ("drm/amd/display: Reinit DPG when exiting dynamic ODM") Reviewed-by:
Dillon Varone <dillon.varone@amd.com> Acked-by:
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Fudong Wang authored
A benchmark stress test (12-40 machines x 48hours) found that DCN315 has cases where DC writes to an indirect register to set the smu clock msg id, but when we go to read the same indirect register the returned msg id doesn't match with what we just set it to. So, to fix this retry the write until the register's value matches with the requested value. Cc: stable@vger.kernel.org # 6.1+ Fixes: f9490399 ("drm/amd/display: Add DCN315 CLK_MGR") Reviewed-by:
Charlene Liu <charlene.liu@amd.com> Acked-by:
Fudong Wang <fudong.wang@amd.com> Signed-off-by:
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Ethan Bitnun authored
- Override the det to adjust microschedule timings allow for 1080p configs with SubVP - To lower unnecessary risk, we prevent multi 1080p configs from using SubVP, as multi 1080p already has low idle power. - Count the number of streams to verify that we are in a SubVP config before overriding Reviewed-by:
Alvin Lee <alvin.lee2@amd.com> Acked-by:
Ethan Bitnun <ethan.bitnun@amd.com> Signed-off-by:
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Lijo Lazar authored
For APUs with SMU v13.0.6, mode-2 reset is kept as default and for others mode-1 is the default reset method. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Asad Kamal <asad.kamal@amd.com> Tested-by:
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Wenjing Liu authored
This partially reverts commit 460ea898 ("drm/amd/display: update add plane to context logic with a new algorithm"). The new secondary pipe allocation logic triggers an issue with a specific hardware state transition and causes a frame of corruption when toggling between windowed MPO and ODM desktop only mode. Ideally hwss is supposed to handle this scenario. We are temporarily reverting the logic and investigate the root cause why this transition would cause corruptions. Fixes: 460ea898 ("drm/amd/display: update add plane to context logic with a new algorithm") Reviewed-by:
Martin Leung <martin.leung@amd.com> Acked-by:
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Li Ma authored
This patch will add header files for MP 14.0.0. v2: updates (Alex) Signed-off-by:
Li Ma <li.ma@amd.com> Signed-off-by:
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Lee Jones authored
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell_mgr.c:123: warning: Function parameter or member 'doorbell_index' not described in 'amdgpu_doorbell_index_on_bar' drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell_mgr.c:123: warning: Excess function parameter 'db_index' description in 'amdgpu_doorbell_index_on_bar' Reviewed-by:
Shashank Sharma <shashank.sharma@amd.com> Signed-off-by:
Lee Jones <lee@kernel.org> Signed-off-by:
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Lee Jones authored
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/imu_v11_0.c: In function ‘imu_v11_0_init_microcode’: drivers/gpu/drm/amd/amdgpu/imu_v11_0.c:52:54: warning: ‘_imu.bin’ directive output may be truncated writing 8 bytes into a region of size between 4 and 33 [-Wformat-truncation=] drivers/gpu/drm/amd/amdgpu/imu_v11_0.c:52:9: note: ‘snprintf’ output between 16 and 45 bytes into a destination of size 40 Signed-off-by:
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Lee Jones authored
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c: In function ‘amdgpu_sdma_init_microcode’: drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c:217:64: warning: ‘.bin’ directive output may be truncated writing 4 bytes into a region of size between 0 and 32 [-Wformat-truncation=] drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c:217:17: note: ‘snprintf’ output between 13 and 52 bytes into a destination of size 40 drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c:215:66: warning: ‘snprintf’ output may be truncated before the last format character [-Wformat-truncation=] drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c:215:17: note: ‘snprintf’ output between 12 and 41 bytes into a destination of size 40 Signed-off-by:
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Lee Jones authored
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c: In function ‘amdgpu_ras_sysfs_create’: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:1406:20: warning: ‘_err_count’ directive output may be truncated writing 10 bytes into a region of size between 1 and 32 [-Wformat-truncation=] drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:1405:9: note: ‘snprintf’ output between 11 and 42 bytes into a destination of size 32 Signed-off-by:
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Lee Jones authored
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:516: warning: Function parameter or member 'xcc_id' not described in 'amdgpu_mm_wreg_mmio_rlc' Signed-off-by:
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Lee Jones authored
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/radeon/radeon_ttm.c: In function ‘radeon_bo_move’: drivers/gpu/drm/radeon/radeon_ttm.c:201:27: warning: variable ‘rbo’ set but not used [-Wunused-but-set-variable] Signed-off-by:
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Colin Ian King authored
There is a spelling mistake in variable throtting_events, rename it to throttling_events. Reviewed-by:
Yang Wang <kevinyang.wang@amd.com> Signed-off-by:
Colin Ian King <colin.i.king@gmail.com> Signed-off-by:
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Christophe JAILLET authored
kvzalloc() can be used instead of kvmalloc() + memset() + explicit NULL assignments. It is less verbose and more future proof. Signed-off-by:
Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by:
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Christophe JAILLET authored
Now that there is an explicit flexible array at the end of 'struct amdgpu_bo_list', it can be used to remove amdgpu_bo_list_array_entry() and simplify some macro. Signed-off-by:
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Christophe JAILLET authored
The case where 'num_entries' is too big, is already handled by struct_size(), because kvmalloc() would fail. It will return -ENOMEM instead of -EINVAL, but it is only related to a unlikely to happen sanity check. Signed-off-by:
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Christophe JAILLET authored
'struct amdgpu_bo_list' is really used as if it was ended by a flex array. So make it more explicit and add a 'struct amdgpu_bo_list_entry entries[]' field at the end of the structure. This way, struct_size() can be used when it is allocated. It is less verbose. Signed-off-by:
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Hamza Mahfooz authored
As made mention of in commit 099303e9 ("drm/amd/display: eDP intermittent black screen during PnP"), we need to turn off the display's backlight before powering off an eDP display. Not doing so will result in undefined behaviour according to the eDP spec. So, set DCN301's edp_backlight_control() function pointer to dce110_edp_backlight_control(). Cc: stable@vger.kernel.org Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2765 Fixes: 9c75891f ("drm/amd/display: rework recent update PHY state commit") Suggested-by:
Swapnil Patel <swapnil.patel@amd.com> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Hawking Zhang authored
Disable gfx ras command is needed in some use cases Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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Lijo Lazar authored
Implement the wait for bootloader call back for PSP v13.0 ASICs. Only for ASICs with PSP v13.0.6, it needs an additional check for VBIOS mailbox status. Signed-off-by:
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Hamza Mahfooz authored
fbcon requires that we implement &drm_framebuffer_funcs.dirty. Otherwise, the framebuffer might take a while to flush (which would manifest as noticeable lag). However, we can't enable this callback for non-fbcon cases since it may cause too many atomic commits to be made at once. So, implement amdgpu_dirtyfb() and only enable it for fbcon framebuffers (we can use the "struct drm_file file" parameter in the callback to check for this since it is only NULL when called by fbcon, at least in the mainline kernel) on devices that support atomic KMS. Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: stable@vger.kernel.org # 6.1+ Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2519Reviewed-by:
Mario Limonciello <mario.limonciello@amd.com> Signed-off-by:
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Darren Powell authored
Replace print_clock_levels with emit_clock_levels for arcturus * replace .print_clk_levels with .emit_clk_levels in arcturus_ppt_funcs * added extra parameter int *offset * removed var size, uses arg *offset instead * removed call to smu_cmn_get_sysfs_buf * errors are returned to caller * returns 0 on success additional incidental changes * changed type of var i, now to remove comparing mismatch types * renamed var s/now/cur_value/ * switch statement default now returns -EINVAL * RAS Recovery returns -EBUSY Based on commit b06b48d7 ("amdgpu/pm: Implement emit_clk_levels for navi10") Signed-off-by:
Darren Powell <darren.powell@amd.com> Reviewed-by:
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Evan Quan authored
Fulfill the incomplete SMU13 `pp_dpm_dcefclk` implementation. Reported-by:
Guan Yu <guan.yu@amd.com> Signed-off-by:
Evan Quan <evan.quan@amd.com> Acked-by:
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Evan Quan authored
The voltage offset setting will be applied to the whole v/f curve line instead of per anchor point base. Signed-off-by:
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Jesse Zhang authored
Since the smu firmware has fixed the issue that described in the commit 60d61f4e ("drm/amdgpu/pm: fix the Stable pstate Test in amdgpu_test"). So we only need keep dpm status check in the funciton - smu_v13_0_5_set_soft_freq_limited_range. Signed-off-by:
Jesse Zhang <Jesse.Zhang@amd.com> Reviewed-by:
Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by:
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Kun Liu authored
for older BIOS, smu won't fill average field of gpu_metrics_table, so we acquire average_* from current field. but now average value is available in gpu_metrics_v2_4 Signed-off-by:
Kun Liu <Kun.Liu2@amd.com> Acked-by:
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Srinivasan Shanmugam authored
The val is defined as unsigned int type, if(val<0) is invalid, hence modified its type to ssize_t Fixes the below: drivers/gpu/drm/amd/pm/amdgpu_pm.c:2800:5-8: WARNING: Unsigned expression compared with zero: val < 0 drivers/gpu/drm/amd/pm/amdgpu_pm.c:2813:5-8: WARNING: Unsigned expression compared with zero: val < 0 Cc: Guchun Chen <guchun.chen@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Pan, Xinhui" <Xinhui.Pan@amd.com> Signed-off-by:
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by:
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Alex Deucher authored
Sensor fetching functions should return an signed int to handle errors properly. Reviewed-by:
Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by:
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Mangesh Gadre authored
Update TCP/UTCL1 thrashing control settings v2: updated rev_id check Signed-off-by:
Mangesh Gadre <Mangesh.Gadre@amd.com> Reviewed-by:
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Srinivasan Shanmugam authored
Replace kzalloc(n * sizeof(...), ...) with kcalloc(n, sizeof(...), ...) since kcalloc is the preferred API in case of allocating with multiply. Fixes the below: WARNING: Prefer kcalloc over kzalloc with multiply Cc: Guchun Chen <guchun.chen@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Pan, Xinhui" <Xinhui.Pan@amd.com> Signed-off-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
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Alex Deucher authored
Print both input and avg power. Fixes: 47f1724d ("drm/amd: Introduce `AMDGPU_PP_SENSOR_GPU_INPUT_POWER`") Reviewed-by:
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Philip Yang authored
If mGPUs is on same IOMMU group, or is ram direct mapped, then mGPUs can share the original BO for GTT mapping dma address, without creating new BO from export/import dmabuf. Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Hawking Zhang authored
amdgpu_device_mode1_reset will return gpu mode1_reset succeed (ret = 0) as long as wait_for_bootloader call succeed, regardless of the status reported by smu or psp firmware. This results to driver continue executing recovery even smu or psp fail to perform mode1 reset. Signed-off-by:
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Aric Cyr authored
This version brings along following fixes: - Ensure FS is enabled before sending request to DMUB for FS changes - Add check for PMFW hard min request complete - Save addr update in scratch before flip - Fix static screen detection setting - Write flip addr to scratch reg for subvp - set minimum of VBlank_nom - Correct unit conversion for vstartup - Roll back unit correction - Enable runtime register offset init for DCN32 DMUB - Refactor edp power control - PQ regamma end point - PQ tail accuracy - Expose mall capability Acked-by:
Wayne Lin <wayne.lin@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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