- 21 Jun, 2006 40 commits
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Kelly Daly authored
This patch removes the changes from an earlier patch that disables oProfile for iSeries within the oProfile KConfig (submitted Feb 23, 2006). Checks within the arch init for iSeries, still allowing profiling for timer interrupts (using firmware_has_feature). Signed-off-by:
Kelly Daly <kelly@au.ibm.com> Acked-by:
Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by:
Paul Mackerras <paulus@samba.org>
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Anton Blanchard authored
Support the ibm,extended-*-frequency properties found in recent POWER5 firmware: cpus/PowerPC,POWER5@0/clock-frequency 59aa5880 (1504336000) cpus/PowerPC,POWER5@0/ibm,extended-clock-frequency 00000000 59aa5880 cpus/PowerPC,POWER5@0/timebase-frequency 0b354b10 (188042000) cpus/PowerPC,POWER5@0/ibm,extended-timebase-frequency 00000000 0b354b10 Signed-off-by:Anton Blanchard <anton@samba.org> Signed-off-by:
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Nathan Lynch authored
Don't dereference a device node that isn't there. A "shouldn't happen" case, but someone ran into it with a possibly misconfigured device tree. Signed-off-by:
Nathan Lynch <ntl@pobox.com> Signed-off-by:
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Anton Blanchard authored
Looking for class-code in PCI children breaks with direct slots. Lets just count all children. Signed-off-by:
Olof Johansson <olof@lixom.net> Signed-off-by:
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Anton Blanchard authored
On partitioned PPC64 systems where a partition is given 1/10 of a processor, we have seen mdelay() delaying for 10 times longer than it should. The reason is that the generic mdelay(n) does n delays of 1 millisecond each. However, with 1/10 of a processor, we only get a one-millisecond timeslice every 10ms. Thus each 1 millisecond delay loop ends up taking 10ms elapsed time. The solution is just to use the PPC64 udelay function, which uses the timebase to ensure that the delay is based on elapsed time rather than how much processing time the partition has been given. (Yes, the generic mdelay uses the PPC64 udelay, but the problem is that the start time gets reset every millisecond, and each time it gets reset we lose another 9ms.) Signed-off-by:
Andrew Morton <akpm@osdl.org>
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Arnd Bergmann authored
Floating point exceptions should not be enabled by default, as this setting impacts the performance on some CPUs, in particular the Cell BE. Since the bits are inherited from parent processes, the place to change the default is the thread struct used for init. glibc sets this up correctly per thread in its fesetenv function, so user space should not be impacted by this setting. None of the other common libc implementations (uClibc, dietlibc, newlib, klibc) has support for fp exceptions, so they are unlikely to be hit by this either. There is a small risk that somebody wrote their own application that manually sets the fpscr bits instead of calling fesetenv, without changing the MSR bits as well. Those programs will break with this change. It probably makes sense to change glibc in the future to be more clever about FE bits, so that when running on a CPU where this is expensive, it disables exceptions ASAP, while it keeps them enabled on CPUs where running with exceptions on is cheaper than changing the state often. Signed-off-by:
Arnd Bergmann <arnd.bergmann@de.ibm.com> Signed-off-by:
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Andreas Schwab authored
Avoid duplication of the syscall table for the cell platform. Based on an idea from David Woodhouse. Signed-off-by:
Andreas Schwab <schwab@suse.de> Acked-by:
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Mark A. Greer authored
On Tue, Jun 20, 2006 at 02:01:26PM +1000, Benjamin Herrenschmidt wrote: > On Mon, 2006-06-19 at 13:08 -0700, Mark A. Greer wrote: > > MPC10x-style interrupt controllers have a serial mode that allows > > several interrupts to be clocked in through one INT signal. > > > > This patch adds the software support for that mode. > > You hard code the clock ratio... why not add a separate call to be > called after mpic_init, > something like mpic_set_serial_int(int mpic, int enable, int > clock_ratio) ? How's this? -- MPC10x-style interrupt controllers have a serial mode that allows several interrupts to be clocked in through one INT signal. This patch adds the software support for that mode. Signed-off-by:
Mark A. Greer <mgreer@mvista.com> -- arch/powerpc/sysdev/mpic.c | 20 ++++++++++++++++++++ include/asm-powerpc/mpic.h | 10 ++++++++++ 2 files changed, 30 insertions(+) -- Signed-off-by:
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Linas Vepstas authored
The PCI error recovery code will printk diagnostic info when a PCI error event occurs. Change the messages to include the slot location code, which is how most sysadmins will know the device. Signed-off-by:
Linas Vepstas <linas@austin.ibm.com> Signed-off-by:
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arnd@arndb.de authored
The SPU context save/restore code is currently built for a 4k page size and we provide a _shipped version of it since most people don't have the spu toolchain that is needed to rebuild that code. This patch hardcodes the data structures to a 64k page alignment, which also guarantees 4k alignment but unfortunately wastes 60k of memory per SPU context that is created in the running system. We will follow up on this with another patch to reduce that overhead or maybe redo the context save/restore logic to do this part entirely different, but for now it should make experimental systems work with either page size. Signed-off-by:
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arnd@arndb.de authored
At this time, all flags are invalid. Since we are planning to actually add valid flags in the future, we better check if any were passed by the user. Signed-off-by:
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Masato Noguchi authored
SPU interrupt status must be cleared before handle it. Otherwise, kernel may drop some interrupt packet. Currently, class2 interrupt treated like: 1) call callback to wake up waiting process 2) mask raised mailbox interrupt 3) clear interrupt status I changed like: 1) mask raised mailbox interrupt 2) clear interrupt status 3) call callback to wake up waiting process Clearing status before masking will make spurious interrupt. Thus, it is necessary to hold by steps I described above, I think. Signed-off-by:
Masato Noguchi <Masato.Noguchi@jp.sony.com> Signed-off-by:
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Masato Noguchi authored
added spu_{save,restore}_dump.h to target of 'make clean' Signed-off-by: -
Masato Noguchi authored
This patch remove 'stop_code' -- discarded member of struct spu. It is written at initialize and interrupt, but never read in current implementation. Signed-off-by:
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Geoff Levand authored
This changes the hypervisor abstraction of setting cpu affinity to a higher level to avoid platform dependent interrupt controller routines. I replaced spu_priv1_ops:spu_int_route_set() with a new routine spu_priv1_ops:spu_cpu_affinity_set(). As a by-product, this change eliminated what looked like an existing bug in the set affinity code where spu_int_route_set() mistakenly called int_stat_get(). Signed-off-by:
Geoff Levand <geoffrey.levand@am.sony.com> Signed-off-by:
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Geoff Levand authored
To support muti-platform binaries the spu hypervisor accessor routines must have runtime binding. I removed the existing statically linked routines in spu.h and spu_priv1_mmio.c and created new accessor routines in spu_priv1.h that operate indirectly through an ops struct spu_priv1_ops. spu_priv1_mmio.c contains the instance of the accessor routines for running on raw hardware. Signed-off-by:
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Geoff Levand authored
Creates new config variables PPC_CELL_NATIVE and PPC_IBM_CELL_BLADE. The existing CONFIG_PPC_CELL is now used to denote the generic Cell processor support. PPC_CELL = make descends into platforms/cell PPC_CELL_NATIVE = add bare metal support PPC_IBM_CELL_BLADE = add blade device drivers, etc. Also renames spu_priv1.c to spu_priv1_mmio.c. Signed-off-by:
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arnd@arndb.de authored
The save/restore sequence for SPE contexts currently attempts to save and restore the channel count for SPE channel 1 (the SPU_WriteEventMask channel. But the CBE architecture (section 9.11.2) clearly states that this channel does not have an associated count. Hardware simply ignores the attempt to write this count, but the simulator generates a warning message. WARNING: 279721590: SPE7: Attempt to write channel count for CH 1 with no associated count is ignored. Signed-off-by:
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Jeremy Kerr authored
Clean up create_spu() a little by using kzalloc instead of kmalloc + assignments. Signed-off-by:
Jeremy Kerr <jk@ozlabs.org> Signed-off-by:
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arnd@arndb.de authored
The wbox channel count of an spu is now initialized to four for the saved context. This makes it possible to write to the mailbox right away without waiting for the SPE to become scheduled first. Signed-off-by:
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arnd@arndb.de authored
For performance analysis, it is often interesting to know which physical SPE a thread is currently running on, and, more importantly, if it is running at all. This patch adds a simple attribute to each SPU directory with that information. The attribute is read-only and called 'phys-id'. It contains an ascii string with the number of the physical SPU (e.g. "0x5"), or alternatively the string "0xffffffff" (32 bit -1) when it is not running at all at the time that the file is read. Signed-off-by:
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arnd@arndb.de authored
spufs currently knows only 4k pages and 16M hugetlb pages. Make it use the regular methods for deciding on the SLB bits. Signed-off-by:
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Michael Ellerman authored
spufs_rmdir tries to acquire the spufs root i_mutex, which is already held by spufs_create_thread. This was tracked as Bug #H9512. Signed-off-by:
Michael Ellerman <michael@ellerman.id.au> Signed-off-by:
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arnd@arndb.de authored
A recent change to the way that the mfc file gets mapped made it impossible to map the SPE Multi-Source Synchronization register into user space, but that may be needed by some applications. This restores the missing functionality. Signed-off-by:
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arnd@arndb.de authored
The spu_base module is rather deeply intermixed with the core kernel, so it makes sense to have that built-in. This will let us extend the base in the future without having to export more core symbols just for it. Signed-off-by:
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Jeremy Kerr authored
SPUs are registered as system devices, exposing attributes through sysfs. Since the sysdev includes a kref, we can remove the one in struct spu (it isn't used at the moment anyway). Currently only the interrupt source and numa node attributes are added. Signed-off-by:
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arnd@arndb.de authored
Enable some of the most requested features in defconfig and refresh with the latest powerpc.git Kconfig files. Signed-off-by:
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arnd@arndb.de authored
Checking the priority field to test for irq validity is completely bogus and breaks with future external interrupt controllers. Signed-off-by:
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Benjamin Herrenschmidt authored
This is a first version of support for the Cell BE "Reliability, Availability and Serviceability" features. It doesn't yet handle some of the RAS interrupts (the ones described in iic_is/iic_irr), I'm still working on a proper way to expose these. They are essentially a cascaded controller by themselves (sic !) though I may just handle them locally to the iic driver. I need also to sync with David Erb on the way he hooked in the performance monitor interrupt. So that's all for 2.6.17 and I'll do more work on that with my rework of the powerpc interrupt layer that I'm hacking on at the moment. Signed-off-by:
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Jon Loeliger authored
Signed-off-by:
Kriston Carson <KristonCarson@freescale.com> Signed-off-by:
Xianghua Xiao <x.xiao@freescale.com> Signed-off-by:
Jon Loeliger <jdl@freescale.com> Acked-by:
Jeff Garzik <jeff@garzik.org> Signed-off-by:
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Jon Loeliger authored
The same I2C driver found on 85xx, etc., can be used for 86xx too. Signed-off-by:
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Jon Loeliger authored
Signed-off-by:
Jeff Brown <Jeff.Brown@freescale.com> Signed-off-by:
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Jon Loeliger authored
Signed-off-by:
Wei Zhang <Wei.Zhang@freescale.com> Signed-off-by:
Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by:
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Jon Loeliger authored
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Jon Loeliger authored
Clear the high BATS during load_up_mmu if FTR_HAS_HIGH_BATS. Allow just a bit more time for secondary CPUs to phone home. Signed-off-by:
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Jon Loeliger authored
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Jon Loeliger authored
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Jon Loeliger authored
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Jon Loeliger authored
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Jon Loeliger authored
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