- 30 Oct, 2020 4 commits
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Dennis Li authored
Instead of saving bad pages in amdgpu_ras_reset_gpu, it will reduce the unnecessary calling of amdgpu_ras_save_bad_pages. Signed-off-by:
Dennis Li <Dennis.Li@amd.com> Reviewed-by:
Hawking Zhang <hawking.zhang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Flora Cui authored
for headless NAVI ASICs Signed-off-by:
Flora Cui <flora.cui@amd.com> Reviewed-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
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Flora Cui authored
Navi14 0x7340/C9 SKU has no display and video support, remove them. Signed-off-by:
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Alex Deucher authored
Fixes this warning: drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_ddc.c: In function ‘defer_delay_converter_wa’: drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_ddc.c:285:2: warning: this ‘if’ clause does not guard... [-Wmisleading-indentation] 285 | if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_0080E1 && | ^~ drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_ddc.c:291:3: note: ...this statement, but the latter is misleadingly indented as if it were guarded by the ‘if’ 291 | if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_006037 && | ^~ Reviewed-by:Evan Quan <evan.quan@amd.com> Signed-off-by:
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- 27 Oct, 2020 36 commits
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Alex Deucher authored
This is required for MALL. Was accidently removed in PSR update. Fixes: 48e48e59 ("drm/amd/display: Disable idle optimization when PSR is enabled") Fixes: 52f2e83e ("drm/amdgpu/display: add MALL support (v2)") Acked-by:
Slava Abramov <slava.abramov@amd.com> Signed-off-by:
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Sandeep Raghuraman authored
Create hwmon attribute for vddc, that uses previously declared get_current_vddc() callback if there's an implementation available. Also hides vddc, if there is no implementation for the current chipset (as per Alexander Deucher's suggestion). Signed-off-by:
Sandeep Raghuraman <sandy.8925@gmail.com> Signed-off-by:
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Sandeep Raghuraman authored
Add implementation of get_current_vddc() callback for Sumo. Signed-off-by:
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Sandeep Raghuraman authored
This patch adds a callback for reporting vddc, to the dpm field of the radeon_asic structure. Signed-off-by:
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Alex Deucher authored
It has been confirmed that the SMU metrics table should always reflect the current fan speed even in manual mode. Fixes: f6eb4339 ("drm/amdgpu/swsmu: handle manual fan readback on SMU11") Reviewed-by:
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Alex Deucher authored
Stop registering the SMU i2c bus on navi1x. This leads to instability issues when userspace processes mess with the bus and also seems to cause display stability issues in some cases. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1314 Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1341Reviewed-by:
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Christian König authored
Not used any more. Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
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Huang Rui authored
This patch is to add vangogh apu flag to support more kickers that belongs vangogh series. Signed-off-by:
Huang Rui <ray.huang@amd.com> Acked-by:
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Evan Quan authored
With this, for multiple monitors in sync(e.g. with the same model), mclk switching will be allowed. That helps saving some idle power on some ASICs(e.g. Polaris). Signed-off-by:
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Evan Quan authored
Check chip family also to avoid wrong identification. V2: use the correct macro without AMDGPU prefix Signed-off-by:
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Evan Quan authored
As this is already performed in smu7_set_power_state_tasks(). Signed-off-by:
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Evan Quan authored
Reconfigure smc display settings on vbitimeout change. Signed-off-by:
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Evan Quan authored
Correct the mclk switching setting for multiple displays. Signed-off-by:
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Evan Quan authored
Enable watermark table setting for Polaris. Signed-off-by:
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Evan Quan authored
Fulfill Polaris get_clock_by_type_with_latency(). Signed-off-by:
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Evan Quan authored
Correct Polaris10 setup. Signed-off-by:
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Evan Quan authored
Correct Polaris smc boot level setup. Signed-off-by:
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Evan Quan authored
Correct Polaris10 pcie spc cap setting. Signed-off-by:
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Evan Quan authored
Correct Polaris10 clk/voltage dependence setup. Signed-off-by:
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Evan Quan authored
Populate the correct highest vddc setting on Polaris. Signed-off-by:
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Evan Quan authored
Correct Polaris10 sclk/mclk dpm enablement. Signed-off-by:
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Evan Quan authored
Correct Polaris10 smc voltage controller setup. Signed-off-by:
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Evan Quan authored
Correct Polaris10 platformcaps setup. Signed-off-by:
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Evan Quan authored
Correct Polaris VRconfig setting. Signed-off-by:
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Evan Quan authored
Correct Polaris10 vddc phase control. Signed-off-by:
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Evan Quan authored
Correct Polaris10 avfs fuse setting. Signed-off-by:
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Evan Quan authored
Correct Polaris DIDT enablement. Signed-off-by:
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Evan Quan authored
Correct powertune table setup for Polaris. Signed-off-by:
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Evan Quan authored
Correct sclk/mclk SS support checks. Signed-off-by:
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Evan Quan authored
Add VR shared rail info. Signed-off-by:
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Evan Quan authored
Add mc register table initialization. Signed-off-by:
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Evan Quan authored
Enable edc controller table setting. Signed-off-by:
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Evan Quan authored
Only if the ZeroRPM feature is supported. Signed-off-by:
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Evan Quan authored
By using the saved copy of ro_range_maximum and ro_range_minimum. Correct the setting for "LdoRefSel". Signed-off-by:
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Evan Quan authored
Make the settings more precise. Signed-off-by:
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Evan Quan authored
By moving that in atomfw_read_efuse(). Signed-off-by:
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