- 27 Sep, 2018 40 commits
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Shaoyun Liu authored
Add Vega20 device IDs, device info and enable it in KFD. Signed-off-by:
Shaoyun Liu <Shaoyun.Liu@amd.com> Acked-by:
Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Shaoyun Liu authored
Add Vega20 support in amdgpu_amdkfd_device_probe. Signed-off-by:
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Shaoyun Liu authored
amdgpu_gpuvm_get_process_page_dir should return the page table address in the format expected by the pm4_map_process packet for all ASIC generations. Signed-off-by:
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Shaoyun Liu authored
Vega20 supports 8 SDMA queues per engine Signed-off-by:
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Emily Deng authored
Correct the format For vega10 sriov, the sdma doorbell must be fixed as follow to keep the same setting with host driver, or it will happen conflicts. Signed-off-by:
Emily Deng <Emily.Deng@amd.com> Acked-by:
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Shaoyun Liu authored
Change doorbell assignments to allow routing doorbells for 8 user mode SDMA queues per engine. Signed-off-by:
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Felix Kuehling authored
struct vi_sdma_mqd is defined in vi_structs.h. Signed-off-by:
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Jay Cornwall authored
Wavefront context save data is of interest to userspace clients for debugging static wavefront state. The MQD contains two parameters required to parse the control stack and the control stack itself is kept in the MQD from gfx9 onwards. Add an ioctl to fetch the context save area and control stack offsets and to copy the control stack to a userspace address if it is kept in the MQD. Signed-off-by:
Jay Cornwall <Jay.Cornwall@amd.com> Reviewed-by:
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Felix Kuehling authored
Also save the version in struct kfd_dev so we only need to query it once. Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Signed-off-by:
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Harish Kasiviswanathan authored
This enables KFD_EVENT_TYPE_HW_EXCEPTION notifications to user mode in response to bad opcodes in a CP queue. Signed-off-by:
Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by:
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Emily Deng authored
KFD module doesn't support TONGA SRIOV, if init KFD module in TONGA SRIOV environment, it will let compute ring IB test fail. Signed-off-by:
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Eric Huang authored
Add the flags of properties according to Asic type and pcie capabilities. Signed-off-by:
Eric Huang <JinHuiEric.Huang@amd.com> Signed-off-by:
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Andrey Grodzovsky authored
Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Acked-by:
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Andrey Grodzovsky authored
This reverts commit 9b0df0937a852d299fbe42a5939c9a8a4cc83c55. This commit breaks KCQ IB test and S3 on Polaris 11. Signed-off-by:
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James Zhu authored
When VCN PG state is unchanged, it is unnecessary to reset power gate state Signed-off-by:
James Zhu <James.Zhu@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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zhong jiang authored
kfree has taken the null pointer into account. hence it is safe to remove the redundant null pointer check before kfree. Signed-off-by:
zhong jiang <zhongjiang@huawei.com> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Alex Deucher authored
Print the enabled smc feature mask in amdgpu_pm_info for debugging. Reviewed-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
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Alex Deucher authored
So we can query what features are enabled for debugging. Reviewed-by:
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Alex Deucher authored
So we can query what features are enabled for debugging. Reviewed-by:
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Alex Deucher authored
So we can query what features are enabled for debugging. Reviewed-by:
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Alex Deucher authored
For getting the 64 bit enabled smc feature mask from vega parts. Reviewed-by:
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Alex Deucher authored
For consistency with other asics. Reviewed-by:
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Alex Deucher authored
For consistency with other asics. Reviewed-by:
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Alex Deucher authored
to vega10_smumgr.c. For consistency with other vega parts. Reviewed-by:
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Alex Deucher authored
For consistency with other vega parts. Reviewed-by:
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Nicholas Kazlauskas authored
[Why] The DISPCLK value was previously requested to be 15% higher for all ASICs that went through the dce110 bandwidth code path. As part of a refactoring of dce_clocks and the dce110 set bandwidth codepath this was removed for power saving considerations. That change caused display corruption under certain hardware configurations with Vega10. [How] The 15% DISPCLK increase is brought back but only on dce110 for now. This is should be a temporary workaround until the root cause is sorted out for why this occurs on Vega (or other ASICs, if reported). Tested-by:
Nick Sarnie <sarnex@gentoo.org> Signed-off-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by:
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SivapiriyanKumarasamy authored
[WHY] Previously night light forced a full update by applying a transfer function update regardless of if it was changed. This logic was removed, Now gamma surface updates are only applied when there is also a plane info update, this does not work in cases such as using the night light slider. [HOW] When moving the night light slider we will perform a full update if the gamma has changed and there is a surface, even when the surface has not changed. Also get stream updates in setgamma prior to update planes and stream. Signed-off-by:
SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com> Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Leo Li authored
[Why] The work struct's schedule call was removed a while ago, making this useless. [How] Remove it. Signed-off-by:
Leo Li <sunpeng.li@amd.com> Reviewed-by:
David Francis <David.Francis@amd.com> Acked-by:
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Nicholas Kazlauskas authored
[Why] During suspend under some hardware configurations can result in a series of atomic commits with a NULL stream status - which causes a NULL pointer dereference. This should be guarded. [How] Exit early from the function - if we can't access the stream then there isn't anything that can be done here. Signed-off-by:
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Eric Bernstein authored
[Why] Need to add strere 3D information in VSC [How] Update mod_build_vsc_infopacket with stereo info Signed-off-by:
Eric Bernstein <eric.bernstein@amd.com> Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
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Tony Cheng authored
Signed-off-by:
Tony Cheng <tony.cheng@amd.com> Reviewed-by:
Steven Chiu <Steven.Chiu@amd.com> Acked-by:
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Su Sung Chung authored
[WHY] There are two different variables used to calculate v_update and v_ready, one for validation and the other for performance parameter calculation. Before the variable for validation was used which caused underflow on 1080edp with vsr enabled [HOW] program v_update and v_ready with the variables for performance parameter calculation Signed-off-by:
Su Sung Chung <su.chung@amd.com> Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
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SivapiriyanKumarasamy authored
Parse the native color bit and send it to freesync module for future use Signed-off-by:
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Charlene Liu authored
add pp_smu NULL ptr check Signed-off-by:
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Samson Tam authored
Use link->link_index as index to pipe_ctx[] to get proper link information instead of using index 0 to avoid potential miss matches. Signed-off-by:
Samson Tam <Samson.Tam@amd.com> Reviewed-by:
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Nikola Cornij authored
FPGA doesn't program backend, so we don't need certain link settings (audio stream for example). Signed-off-by:
Nikola Cornij <nikola.cornij@amd.com> Reviewed-by:
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Rex Zhu authored
this can avoid hard hang and be useful for debug. Reviewed-by:
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Rex Zhu authored
Honour display's request for min engine clock/memory clock. Reviewed-by:
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Rex Zhu authored
Revert "drm/amd/display: Remove call to amdgpu_pm_compute_clocks" This reverts commit dcd473770e86517543691bdb227103d6c781cd0a. when display configuration changes, dc need to update the changes to powerplay, also need to trigger a power state task. amdgpu_pm_compute_clocks is the interface to set power state task either dpm enabled or powerplay enabled Acked-by:
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Dave Airlie authored
Sean Paul requested an -rc5 backmerge from some sun4i fixes. Signed-off-by:Dave Airlie <airlied@redhat.com>
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