I am unclear how this got messed up in the shuffle, but it did.

Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

This patch existed before, but was lost over time.

Note that reset is still somewhat problematic in my limited testing (ie.
module_reload will not pass) but it can be disabled with a module
parameter, and support should be considered preliminary anyway.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

Prior to Haswell the CPU control register for backlight
(BLC_PWM_CPU_CTL) toggled the PCH baclight pin for us. This made some
sense as there was no pin on the CPU. With Haswell came the introduction
of a CPU backlight pin, but the interface was still controlled by
software with the same mechnism. Behind the scenes, hardware did all the
dirty work for us.

Broadwell no longer provides this for free. If we want to use the PCH
backlight pin [1] then we have to set the override bit BLC_PWM_PCH_CTL1
and program BLC_PWM_PCH_CTL2 for the PWM values.

This patch implements that. This patch is compile tested only, and given
that I rarely if ever touch this code, careful review is welcome.

[1] According to Art, we know of no devices that exist which use the CPU
pin (and remember it has existed already on HSW). If such a device does
exist, we'll have to handle it properly - this is left as TODO until
then.

v2: Drop the abstraction prep patch, as a bigger backlight overhaul is
    in the works, and do just the mimimal bdw enabling now. (by Jani)

CC: Art Runyan <arthur.j.runyan@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

For what we care about ULT and ULX are interchangeable. We know of 3
types of pciids for these cases. I am not sure if at some point we will
need to distinguish ULT and ULX.

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

One last patch I keep forgetting to include.  Fix for EDID quirk
handling.  Been on the list and reviewed for several months now,
I just keep forgetting about it.

* 'drm-next-3.13' of git://people.freedesktop.org/~agd5f/linux:
  drm/edid: compare actual vrefresh for all modes for quirks

Merge tag 'drm-intel-fixes-2013-11-12' of git://people.freedesktop.org/~danvet/drm-intel into drm-next

Just one patch to fix compile fail for CONFIG_ACPI=n. Figured I better
send this out quickly to minimize the broken build span. Otherwise no
bugfixes (besides some bdw stuff) anywhere in sight.

* tag 'drm-intel-fixes-2013-11-12' of git://people.freedesktop.org/~danvet/drm-intel:
  drm/i915/opregion: fix build error on CONFIG_ACPI=n

The page-prot bit fix.

* 'ttm-next-3.13' of git://people.freedesktop.org/~thomash/linux:
  drm/ttm: Fix vma page_prot bit manipulation

A resource eviction fix, and a fix for compilation / sparse problems
from the previous pull.

* 'vmwgfx-next-3.13' of git://people.freedesktop.org/~thomash/linux:
  drm/vmwgfx: Fix a couple of compile / sparse warnings and errors
  drm/vmwgfx: Resource evict fixes

Fix a long-standing TTM issue where we manipulated the vma page_prot
bits while mmap_sem was taken in read mode only. We now make a local
copy of the vma structure which we pass when we set the ptes.
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>

Fixes
 *) an implicit function declaration on mips,
 *) a defined but not used label on !CONFIG_INTEL_IOMMU
 *) Hopefully a couple of sparse warnings where we implicitly typecast
    integer to __le32 and vice versa.
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

Fix an error message that was incorrectly blaming device resource id
shortage.

Also make sure we correctly catch resource eviction errors, that
could otherwise lead to evictable resources temporarily not being on the
LRU list.
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Jakob Bornecrantz <jakob@vmware.com>
Cc: stable@vger.kernel.org

The vrefresh field of the mode is 0 for most modes
fetched from the EDID (e.g., established timings).
When dealing with monitors that have a bogus preferred
mode, we may not always select the mode we want because
we compare the target refresh to the mode's vrefresh which
is 0 in a lot of cases.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

SDVO support for minnowboard

* 'gma500-next' of git://github.com/patjak/drm-gma500:
  drm/gma500/mrst: Add SDVO to output init
  drm/gma500/mrst: Don't blindly guess a mode for LVDS
  drm/gma500/mrst: Setup GMBUS for oaktrail/mrst
  drm/gma500/mrst: Replace WMs and chickenbits with values from EMGD
  drm/gma500/mrst: Add aux register writes to SDVO
  drm/gma500/mrst: Properly route oaktrail hdmi hooks
  drm/gma500/mrst: Add aux register writes when programming pipe
  drm/gma500/mrst: Add SDVO clock calculation
  drm/gma500: Add aux device support for gmbus
  drm/gma500: Add support for aux pci vdc device
  drm/gma500: Add chip specific sdvo masks
  drm/gma500: Add Minnowboard to the IS_MRST() macro

Turn clk_enable() and clk_disable() calls into clk_prepare_enable() and
clk_disable_unprepare() to get ready for the migration to the common
clock framework.

Cc: David Airlie <airlied@linux.ie>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

Merge tag 'bdw-stage1-2013-11-08-v2' of git://people.freedesktop.org/~danvet/drm-intel into drm-next

So here's the Broadwell pull request. From a kernel driver pov there's
two areas with big changes in Broadwell:
- Completely new enumerated interrupt bits. On the plus side it now looks
  fairly unform and sane.
- Completely new pagetable layout.

To ensure minimal impact on existing platforms we've refactored both the
irq and low-level gtt handling code a lot in anticipation of the bdw push.
So now bdw enabling in these areas just plugs in a bunch of vfuncs.

Otherwise it's all fairly harmless adjusting of switch cases and
if-ladders to shovel bdw into the right blocks. So minimized impact on
existing platforms. I've also merged the bdw-stage1 branch into our
-nightly integration branch for the past week to make sure we don't break
anything.

Note that there's still quite a flurry or patches floating around, but
I've figured I'll push this out. I plan to keep the bdw fixes separate
from my usual -fixes stream so that you can reject them easily in case it
still looks like too much churn. Also, bdw is for now hidden behind the
preliminary hw enabling module option. So there's no real pressure to get
follow-up patches all into 3.13.

* tag 'bdw-stage1-2013-11-08-v2' of git://people.freedesktop.org/~danvet/drm-intel: (75 commits)
  drm/i915: Mask the vblank interrupt on bdw by default
  drm/i915: Wire up cpu fifo underrun reporting support for bdw
  drm/i915: Optimize gen8_enable|disable_vblank functions
  drm/i915: Wire up pipe CRC support for bdw
  drm/i915: Wire up PCH interrupts for bdw
  drm/i915: Wire up port A aux channel
  drm/i915: Fix up the bdw pipe interrupt enable lists
  drm/i915: Optimize pipe irq handling on bdw
  drm/i915/bdw: Take render error interrupt out of the mask
  drm/i915/bdw: Add BDW PCH check first
  drm/i915: Use hsw_crt_get_config on BDW
  drm/i915/bdw: Change dp aux timeout to 600us on DDIA
  drm/i915/bdw: Enable trickle feed on Broadwell
  drm/i915/bdw: WaSingleSubspanDispatchOnAALinesAndPoints
  drm/i915/bdw: conservative SBE VUE cache mode
  drm/i915/bdw: Limit SDE poly depth FIFO to 2
  drm/i915/bdw: Sampler power bypass disable
  ddrm/i915/bdw: Disable centroid pixel perf optimization
  drm/i915/bdw: BWGTLB clock gate disable
  drm/i915/bdw: Implement edp PSR workarounds
  ...

A few more patches for 3.13.  The big one here is Hawaii support.
I wanted to get that out sooner, but was sick earlier this week.  That
said, it's mostly self contained, so it shouldn't impact other asics.
The rest are just bug fixes and a merge fix.

* 'drm-next-3.13' of git://people.freedesktop.org/~agd5f/linux: (23 commits)
  Revert "drm/radeon/audio: don't set speaker allocation on DCE4+"
  drm/radeon/audio: improve ACR calculation
  drm/radeon/audio: correct ACR table
  drm/radeon: fix mismerge of drm-next with 3.12
  drm/radeon: add pci ids for hawaii
  drm/radeon: fill in radeon_asic_init for hawaii
  drm/radeon: modesetting updates for hawaii
  drm/radeon: atombios.h updates for hawaii
  drm/radeon: update cik_get_csb_buffer for hawaii
  drm/radeon: add hawaii dpm support
  drm/radeon/cik: add hawaii UVD support
  drm/radeon: update firmware loading for hawaii
  drm/radeon: update rb setup for hawaii
  drm/radeon: add golden register settings for hawaii
  drm/radeon: update cik_tiling_mode_table_init() for hawaii
  drm/radeon: minor updates to cik.c for hawaii
  drm/radeon: update cik_gpu_init() for hawaii
  drm/radeon: add Hawaii chip family
  drm/radeon: fix-up some float to fixed conversion thinkos
  drm/radeon: use HDP_MEM_COHERENCY_FLUSH_CNTL for sdma as well
  ...

prime support, inactive rework, render nodes
* 'msm-next' of git://people.freedesktop.org/~robclark/linux:
  drm/msm/mdp4: page_flip cleanups/fixes
  drm/msm: EBUSY status handling in msm_gem_fault()
  drm/msm: rework inactive-work
  drm/msm: add plane support
  drm/msm: resync generated headers
  drm/msm: support render nodes
  drm/msm: prime support

This uses the proper div macro.
Signed-off-by: Dave Airlie <airlied@redhat.com>

Fix CONFIG_ACPI=n build fail

  CC      drivers/gpu/drm/i915/intel_opregion.o
drivers/gpu/drm/i915/intel_opregion.c: In function ‘intel_opregion_setup’:
drivers/gpu/drm/i915/intel_opregion.c:879:2: error: ‘asle_work’ undeclared (first use in this function)
drivers/gpu/drm/i915/intel_opregion.c:879:2: note: each undeclared identifier is reported only once for each function it appears in
make[4]: *** [drivers/gpu/drm/i915/intel_opregion.o] Error 1

introduced in
commit 91a60f20
Author: Jani Nikula <jani.nikula@intel.com>
Date:   Thu Oct 31 18:55:48 2013 +0200

    drm/i915: move opregion asle request handling to a work queue
Reported-by: Jim Davis <jim.epost@gmail.com>
Reference: http://lkml.kernel.org/r/CA+r1ZhjcFpr5KKVX0pLCOP8cAyZoiYO=UyqYMJtNSV-Kt_p7xQ@mail.gmail.comSigned-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

This reverts commit 555b1b65.

Let's try this again for 3.13.  It's required for proper
interaction with alsa.  Was disabled previously in 3.12
to be on the safe side since it caused problems on older
asics.

In order to have any realistic chance of calculating proper
ACR values, we need to be able to calculate both N and CTS,
not just CTS. We still aim for the ideal N as specified in
the HDMI spec though.

bug:
https://bugs.freedesktop.org/show_bug.cgi?id=69675Signed-off-by: Pierre Ossman <pierre@ossman.eu>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

The values were taken from the HDMI spec, but they assumed
exact x/1.001 clocks. Since we round the clocks, we also need
to calculate different N and CTS values.

Note that the N for 25.2/1.001 MHz at 44.1 kHz audio is out of
spec. Hopefully this mode is rarely used and/or HDMI sinks
tolerate overly large values of N.

bug:
https://bugs.freedesktop.org/show_bug.cgi?id=69675Signed-off-by: Pierre Ossman <pierre@ossman.eu>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Audio is enabled by default now.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

This adds the pci ids for hawaii.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Fill in gpu details for hawaii.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Uses the same code as bonaire.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

This updates atombios.h with the latest changes
required for hawaii.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Set the PA_SC_RASTER_CONFIG[_1] registers for hawaii.
The rest is the same as the other asics.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

This updates the CI dpm (dynamic power management)
support for hawaii.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Has same version of UVD as other CIK parts.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

This just updates the firmware loading functions
to look for the appropriate firmware files for
hawaii.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

The formula needs to be adjusted since there are 4 RBs
per SH rather than 2 as on previous asics.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

The golden register settings are optimal settings for
certain registers from the hardware team.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Hawaii uses a different tiling configuration.  Add support
for it.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Skip programming a register that was removed and
adjust the mask of the VM client status.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

This adds the hawaii asic specific configuration
details.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Hawaii is a new CI-based dGPU.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Spotted by Brad Smith when porting to OpenBSD.
Noticed-by: Brad Smith <brad@comstyle.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

The new HDP flush method doesn't seem to work reliably on
sDMA either, so use the old method here too.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

To plug the VRAM memory leak (see previous patch for
details) we must unpin the frame buffer when disabling the
CRTC. This warrants the addition of disable function for legacy
CRTC, which puts the CRTC in DPMS-OFF state and unpins the
frame buffer if there is one associated with the CRTC.
Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>