- 23 Mar, 2023 5 commits
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Neil Armstrong authored
The first QMP PHY is an USB3/DP combo phy, switch to the newly documented bindings and register the clocks to the GCC and DISPCC controllers. Reviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> #SM8350-HDK Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230206-topic-sm8450-upstream-dp-controller-v6-2-d78313cbc41d@linaro.org
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Krzysztof Kozlowski authored
Device node names should be generic and bindings expect certain pattern for RPMh regulator nodes. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by:
Douglas Anderson <dianders@chromium.org> Reviewed-by:
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Krzysztof Kozlowski authored
Bindings expect DBVDD-supply and LDO1-IN-supply: sc7280-herobrine-evoker-lte.dtb: codec@1a: 'DBVDD-supply' is a required property sc7280-herobrine-evoker-lte.dtb: codec@1a: 'LDO1-IN-supply' is a required property In sc7180-trogdor.dtsi they come from the same regulator, so let's assume intention was the same here. Signed-off-by:
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Krzysztof Kozlowski authored
It seems that the RT5682S codec does not use VBAT-supply: sc7180-trogdor-pazquel360-lte.dtb: codec@1a: Unevaluated properties are not allowed ('VBAT-supply' was unexpected) Signed-off-by: -
Kathiravan T authored
Add the APCS, A53 PLL, cpu-opp-table nodes to bump the CPU frequency above 800MHz. Signed-off-by:
Kathiravan T <quic_kathirav@quicinc.com> Signed-off-by:
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- 22 Mar, 2023 34 commits
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Johan Hovold authored
Describe the bus topology for PCIe domain 6 and add the ath11k calibration variant so that the board file (calibration data) can be loaded. Link: https://bugzilla.kernel.org/show_bug.cgi?id=216246Reviewed-by:
Steev Klimaszewski <steev@kali.org> Signed-off-by:
Johan Hovold <johan+linaro@kernel.org> Signed-off-by:
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Johan Hovold authored
All the input devices use s10b as 1.8V supply. Signed-off-by:
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Johan Hovold authored
The s11b, s12b, s1c and bob supplies are used by several pmic regulators. Add the missing description to the devicetree. Note that there are still some consumers that are not (fully) described in the devicetree so the supplies must remain marked as always-on for now. Signed-off-by:
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Krzysztof Kozlowski authored
Downstream DTS uses 16 mA drive strength for the WCD9385 audio codec RESET_N reset pin. It also pulls the pin down in shutdown mode, thus it is more like a shutdown pin, not a reset. Use the same settings here for HDK8450 and keep the WCD9385 by default in powered off (so pin as low). Align the name of pin configuration node with other pins in the DTS. Signed-off-by:
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Krzysztof Kozlowski authored
The HDK8450 uses WCD9385 audio codec, so use precise compatible, even though WCD9380 and WCD9385 are both compatible. Signed-off-by:
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Krzysztof Kozlowski authored
Downstream DTS (and sc8280xp-lenovo-thinkpad-x13s with the same speakers) uses 16 mA drive strength for the WSA8835 speaker SD_N reset/shutdown pin. Use the same for HDK8450, as it is seem the recommended value. Signed-off-by:
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Konrad Dybcio authored
Add a SoC-specific compatbile to cpufreq_hw for compliancy with bindings. Signed-off-by:
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Konrad Dybcio authored
Add a SoC-specific compatbile to cpufreq_hw for compliancy with bindings. Signed-off-by:
Luca Weiss <luca.weiss@fairphone.com> Signed-off-by:
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Konrad Dybcio authored
Add a SoC-specific compatbile to cpufreq_hw for compliancy with bindings. Signed-off-by:
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Konrad Dybcio authored
Add a SoC-specific compatbile to cpufreq_hw for compliancy with bindings. Signed-off-by:
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Konrad Dybcio authored
Add a SoC-specific compatbile to cpufreq_hw for compliancy with bindings. Signed-off-by:
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Gergo Koteles authored
Enable the Hall effect sensor (flip cover) for OnePlus 6/6T. The GPIO is mapped to SW_LID events as in msm8916, msm8994, msm8998 devices. Signed-off-by:
Gergo Koteles <soyer@irl.hu> Reviewed-by:
Caleb Connolly <caleb@connolly.tech> Reviewed-by:
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Krzysztof Kozlowski authored
Remove trailing, redundant line breaks. Signed-off-by:
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Krzysztof Kozlowski authored
Drop empty override of pm8998_gpios. Signed-off-by:
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Krzysztof Kozlowski authored
Bindings expect thermal node names to end with '-thermal', so fix pm660 and pm660l: sda660-inforce-ifc6560.dtb: thermal-zones: 'pm660', 'pm660l' do not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-]{1,12}-thermal$', 'pinctrl-[0-9]+' Signed-off-by: -
Krzysztof Kozlowski authored
The "dr_mode" is a property of USB DWC3 node, not the Qualcomm wrapper one: sm8350-microsoft-surface-duo2.dtb: usb@a6f8800: 'dr_mode' does not match any of the regexes: '^usb@[0-9a-f]+$', 'pinctrl-[0-9]+' Fixes: c16160cf ("arm64: dts: qcom: add minimal DTS for Microsoft Surface Duo 2") Signed-off-by:
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Krzysztof Kozlowski authored
Fix typo in USB DWC3 node maximum speed property. Fixes: a41b6175 ("arm64: dts: qcom: sm8250: Add device tree for Xiaomi Mi Pad 5 Pro") Signed-off-by:
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Bartosz Golaszewski authored
Enable the high-speed UART port connected to the Bluetooth controller on the sa8775p-adp development board. Signed-off-by:
Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by:
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Bartosz Golaszewski authored
Enable the high-speed UART port connected to the GNSS controller on the sa8775p-adp development board. Signed-off-by:
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Bartosz Golaszewski authored
Add two UART nodes that are known to be used by existing development boards with this SoC. Signed-off-by:
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Bartosz Golaszewski authored
Enable the SPI interface exposed on the sa8775p-ride development board. Signed-off-by:
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Bartosz Golaszewski authored
Add the SPI controller node for the interface exposed on the sa8775p-ride development board. Signed-off-by:
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Bartosz Golaszewski authored
This enables the I2C interface on the sa8775p-ride development board. Signed-off-by:
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Bartosz Golaszewski authored
Add a disabled node for the I2C interface that's exposed on the sa8775p-ride development board. Signed-off-by:
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Bartosz Golaszewski authored
Enable the second instance of the QUPv3 engine on the sa8775p-ride board. Signed-off-by:
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Bartosz Golaszewski authored
Add the second instance of the QUPv3 engine to the sa8775p.dtsi. Signed-off-by:
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Danila Tikhonov authored
Add a node describing the flash block found on pm8150l. Signed-off-by:
Danila Tikhonov <danila@jiaxyga.com> Signed-off-by:
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Bhupesh Sharma authored
As per documentation, Qualcomm SDM845 SoC supports BAM DMA engine v1.7.4, so use the correct compatible strings. Signed-off-by:
Bhupesh Sharma <bhupesh.sharma@linaro.org> Reviewed-by:
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Neil Armstrong authored
Add the pmic glink node linked with the DWC3 USB controller switched to OTG mode and tagged with usb-role-switch. Reviewed-by:
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Neil Armstrong authored
Add the pmic glink node linked with the DWC3 USB controller switched to OTG mode and tagged with usb-role-switch. Reviewed-by:
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Neil Armstrong authored
Add the pmic glink node linked with the DWC3 USB controller switched to OTG mode and tagged with usb-role-switch. Signed-off-by:
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Neil Armstrong authored
Add ports subnodes in dwc3 node to avoid repeating the same description in each board DT. Reviewed-by:
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Neil Armstrong authored
Add ports subnodes in dwc3 node to avoid repeating the same description in each board DT. Reviewed-by:
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Neil Armstrong authored
Add ports subnodes in dwc3 node to avoid repeating the same description in each board DT. Reviewed-by:
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- 20 Mar, 2023 1 commit
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Bhupesh Sharma authored
Normally the 'pinctrl' properties of a SDHC controller and the chip detect pin settings are dependent on the type of the slots (for e.g uSD card slot), regulators and GPIO(s) available on the board(s). So, move the same from the sm6115 dtsi file to the respective board file(s). Reviewed-by:
Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by:
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