- 25 Aug, 2021 4 commits
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Ville Syrjälä authored
Lots of places don't need to modify the DPLL params, so make them const. Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210715093530.31711-5-ville.syrjala@linux.intel.comReviewed-by:
Jani Nikula <jani.nikula@intel.com>
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Ville Syrjälä authored
Make the PCH dpll code match the gmch code by splitting the FP register handling out from ilk_compute_dpll(). Signed-off-by:
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Ville Syrjälä authored
The current gen2 DPLL readout code: * assumes i845/i865 have LVDS which is not true * assumes only pipe B can drive LVDS (true, but makes the code appear a bit magical) * hard to parse in general Clean it up by checking for i85x (the only gen2 platform with LVDS) and reusing intel_lvds_port_enabled(). Signed-off-by:
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Ville Syrjälä authored
When we enable the DPLL for the PPS kick, let's tell the DPLL code we're dealing with an eDP output. This shouldn't really matter, but it's more consistent with the way the DPLL is configured when we're actually enabling the eDP port for real. Signed-off-by:
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- 24 Aug, 2021 15 commits
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Ville Syrjälä authored
We don't care about __iomem mismatch when dealing with error pointers. Silence it with ERR_CAST(). drivers/gpu/drm/i915/display/intel_dpt.c:136:21: warning: incorrect type in assignment (different address spaces) drivers/gpu/drm/i915/display/intel_dpt.c:136:21: expected struct i915_vma *[assigned] vma drivers/gpu/drm/i915/display/intel_dpt.c:136:21: got void [noderef] __iomem *[assigned] iomem v2: The code moved into intel_dpt.c Signed-off-by:
Matthew Auld <matthew.auld@intel.com>
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Jani Nikula authored
Split out fb related stuff from intel_display.c to intel_fb.c. Reviewed-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
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Jani Nikula authored
Split out fb related stuff from intel_display.c to intel_fb.c. Reviewed-by:
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Jani Nikula authored
Split out fb related stuff from intel_display.c to intel_fb.c. Reviewed-by:
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Jani Nikula authored
Split out fb related stuff from intel_display.c to intel_fb.c. Reviewed-by:
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Jani Nikula authored
This will be needed in multiple places soon. Reviewed-by:
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Jani Nikula authored
Let's try to reduce the size of intel_display.c, not increase it. Reviewed-by:
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Jani Nikula authored
The unsigned doesn't help us here. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Suggested-by:
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Swati Sharma authored
drm_dp_dpcd_read/write already has debug error message. Drop redundant error messages which gives false status even if correct value is read in drm_dp_dpcd_read(). v2: -Added fixes tag (Ankit) v3: -Fixed build error (CI) Fixes: 9488a030 ("drm/i915: Add support for enabling link status and recovery") Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Sean Paul <seanpaul@chromium.org> Cc: Uma Shankar <uma.shankar@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: <stable@vger.kernel.org> # v5.12+ Reviewed-by:
Swati Sharma <swati2.sharma@intel.com> Signed-off-by:
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Jani Nikula authored
DP 2.0 UHBR link rates always use 128b/132b channel encoding, which has a different data bandwidth efficiency from 8b/10b. The computation is slightly convoluted due to the units we use; this is all explained in the added comment. v2: Clarified comment (Manasi) Reviewed-by:
Manasi Navare <manasi.d.navare@intel.com> Signed-off-by:
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Jani Nikula authored
DG2 supports DP 2.0 UHBR and 128b/132b channel encoding. Bspec: 53657, 54034 Acked-by:
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Jani Nikula authored
Add the registers for specifying the lower and higher 24 bits of the DP 2.0 pixel clock frequency in Hz. Bspec: 53326 Reviewed-by:
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Jani Nikula authored
This register controls the DP 2.0 datapath. Bspec: 69967 Reviewed-by:
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Jani Nikula authored
See if sink supports DP 2.0 128b/132b channel encoding, and update sink rates accordingly. FIXME: Also take LTTPR 128b/132b into account. v2: Add build-time check for ->sink_rates size (Ville) Reviewed-by:
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Jani Nikula authored
The MST code uses actual link rates in the limits struct, while the DP code in general uses indexes to the ->common_rates[] array. Fix the confusion by using actual link rate values everywhere. This is a better abstraction than some obscure index. Rename the struct members while at it to ensure all the places are covered. Reviewed-by:
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- 23 Aug, 2021 1 commit
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Tejas Upadhyay authored
Sync PCI IDs with Bspec. Bspec:53655 Changes since V2: - Upstream devices which are "POR" yes and "Ok to upstream" yes - James Asmus Changes since V1: - All POR and Non POR Ids needs to be upstreamed - James Asmus Signed-off-by:Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> Reviewed-by:
José Roberto de Souza <jose.souza@intel.com> Signed-off-by:
Anshuman Gupta <anshuman.gupta@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210818050116.1116237-1-tejaskumarx.surendrakumar.upadhyay@intel.com
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- 20 Aug, 2021 10 commits
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Kai-Heng Feng authored
Users reported that after commit 2bbd6dba ("drm/i915: Try to use fast+narrow link on eDP again and fall back to the old max strategy on failure"), the screen starts to have wobbly effect. Commit a5c936ad ("drm/i915/dp: Use slow and wide link training for everything") doesn't help either, that means the affected eDP 1.2 panels only work with max params. So use max params for panels < eDP 1.4 as Windows does to solve the issue. v3: - Do the eDP rev check in intel_edp_init_dpcd() v2: - Check eDP 1.4 instead of DPCD 1.1 to apply max params Cc: stable@vger.kernel.org Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/3714 Fixes: 2bbd6dba ("drm/i915: Try to use fast+narrow link on eDP again and fall back to the old max strategy on failure") Fixes: a5c936ad ("drm/i915/dp: Use slow and wide link training for everything") Suggested-by:
Kai-Heng Feng <kai.heng.feng@canonical.com> Signed-off-by:
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Ville Syrjälä authored
Polish the FBC stride override stuff: - just call it override_cfb_stride since it'll be used on more gens later - Use REG_BIT() & co. for the registers and give everything CHICKEN_ prefix since glk+ will have a different register for this - Use intel_de_rmw() for the RMW Signed-off-by:
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Ville Syrjälä authored
On ILK+ we current do a nuke right after activating FBC. If my memory isn't playing tricks on me this is actially required if FBC didn't stay disabled for a full frame. In that case the deactivate+reactivate may not invalidate the cfb. I'd have to double chekc to be sure though. So let's keep the nuke, and just extend it backwards to cover all the platforms by doing it a bit higher up. Reviewed-by:
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Ville Syrjälä authored
Pull the fbc enable vs. disable stuff into a small helper so we don't have to have it pollute the higher level modeset code. Reviewed-by:
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Ville Syrjälä authored
Write the tiling check in a nicer form. No functional changes due to Y-tile scanout being a gen9+ feature. Reviewed-by:
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Jani Nikula authored
There's no performance reason to have it as static inline; move it out of intel_display_types.h to reduce clutter and dependency on i915_drv.h. Reviewed-by:
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Jani Nikula authored
There's no performance reason to have it as static inline; move it out of intel_display_types.h to reduce clutter and dependency on i915_drv.h. Reviewed-by:
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Jani Nikula authored
The fewer includes the better. Reviewed-by:
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Jani Nikula authored
Reduce includes. Reviewed-by:
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Jani Nikula authored
Presumably if the compiler is smart, it does not generate an extra function call to the update functions that are now static. Reviewed-by:
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- 18 Aug, 2021 2 commits
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Matt Roper authored
One of the cases that the bspec lists for when underrun recovery must be disabled is "COG;" that note actually refers to eDP multi-segmented operation (MSO). Let's ensure the this additional restriction is honored by the driver. Bspec: 50351 Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Fixes: ba3b049f ("drm/i915/adl_p: Allow underrun recovery when possible") Signed-off-by:
Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210816204112.2960624-1-matthew.d.roper@intel.comReviewed-by:
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Lee Shawn C authored
After DPRX link training, intel_dp_link_train_phy() did not return the training result properly. If link training failed, i915 driver would not run into link train fallback function. And no hotplug uevent would be received by user space application. Fixes: b30edfd8 ("drm/i915: Switch to LTTPR non-transparent mode link training") Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Cooper Chiou <cooper.chiou@intel.com> Cc: William Tseng <william.tseng@intel.com> Signed-off-by:
Lee Shawn C <shawn.c.lee@intel.com> Reviewed-by:
Imre Deak <imre.deak@intel.com> Signed-off-by:
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- 16 Aug, 2021 5 commits
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José Roberto de Souza authored
There is no users of it, so no need to keep handling for it. Reviewed-by:
Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Signed-off-by:
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José Roberto de Souza authored
skl_calc_main_surface_offset() is used to calculate an aligned plane surface address considering the inner framebuffer x and y offset. It can not be used by selective fetch functions becase there is no PLANE_SEL_FETCH_SURF. So the PLANE_SEL_FETCH_OFFSET.y should only be PLANE_OFFSET.y + damaged_area_within_plane.y1. This fixes glitches seen in fbcon caused by typing something in the terminal. BSpec: 55229 Reviewed-by:
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Jani Nikula authored
The symbol isn't needed outside of i915.ko. Fixes: b30edfd8 ("drm/i915: Switch to LTTPR non-transparent mode link training") Fixes: 264613b4 ("drm/i915: Disable LTTPR support when the DPCD rev < 1.4") Cc: Imre Deak <imre.deak@intel.com> Reviewed-by:
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Jani Nikula authored
Catch up with drm core changes. Signed-off-by: -
git://anongit.freedesktop.org/drm/drm-miscDave Airlie authored
drm-misc-next for v5.15: UAPI Changes: Cross-subsystem Changes: - Add lockdep_assert(once) helpers. Core Changes: - Add lockdep assert to drm_is_current_master_locked. - Fix typos in dma-buf documentation. - Mark drm irq midlayer as legacy only. - Fix GPF in udmabuf_create. - Rename member to correct value in drm_edid.h Driver Changes: - Build fix to make nouveau build with NOUVEAU_BACKLIGHT. - Add MI101AIT-ICP1, LTTD800480070-L6WWH-RT panels. - Assorted fixes to bridge/it66121, anx7625. - Add custom crtc_state to simple helpers, and use it to convert pll handling in mgag200 to atomic. - Convert drivers to use offset-adjusted framebuffer bo mappings. - Assorted small fixes and fix for a use-after-free in vmwgfx. - Convert remaining callers of non-legacy drivers to use linux irqs directly. - Small cleanup in ingenic. - Small fixes to virtio and ti-sn65dsi86. Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1cf2d7fc-402d-1852-574a-21cbbd2eaebf@linux.intel.com
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- 13 Aug, 2021 3 commits
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Jani Nikula authored
UHBR link rates use different tx equalization settings. Using this will require changes in the link training code too. Bspec: 53920 Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Reviewed-by:
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Jani Nikula authored
We use encoder->get_buf_trans() in many places, for example intel_ddi_dp_voltage_max(), and the hook was set to some old platform's function for DG2 SNPS PHY. Convert SNPS PHY to use the same translation mechanisms as everything else. Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Reviewed-by:
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Jani Nikula authored
Needed in the future. Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Reviewed-by:
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