- 29 Jun, 2017 19 commits
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Paul Burton authored
This patch switches MIPS to make use of generically implemented queued read/write locks, rather than the custom implementation used previously. This allows us to drop a whole load of inline assembly, share more generic code, and is also a performance win. Results from running the AIM7 short workload on a MIPS Creator Ci40 (ie. 2 core 2 thread interAptiv CPU clocked at 546MHz) with v4.12-rc4 pistachio_defconfig, with ftrace disabled due to a current bug, and both with & without use of queued rwlocks & spinlocks: Forks | v4.12-rc4 | +qlocks | Change -------|-----------|----------|-------- 10 | 52630.32 | 53316.31 | +1.01% 20 | 51777.80 | 52623.15 | +1.02% 30 | 51645.92 | 52517.26 | +1.02% 40 | 51634.88 | 52419.89 | +1.02% 50 | 51506.75 | 52307.81 | +1.02% 60 | 51500.74 | 52322.72 | +1.02% 70 | 51434.81 | 52288.60 | +1.02% 80 | 51423.22 | 52434.85 | +1.02% 90 | 51428.65 | 52410.10 | +1.02% The kernels used for these tests also had my "MIPS: Hardcode cpu_has_* where known at compile time due to ISA" patch applied, which allows the kernel_uses_llsc checks in cmpxchg() & xchg() to be optimised away at compile time. Signed-off-by:Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16357/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Paul Burton authored
The __xchg() function declares its first 2 arguments in reverse order compared to the xchg() macro, which is confusing & serves no purpose. Reorder the arguments such that __xchg() & xchg() match. Signed-off-by:
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Paul Burton authored
Implement support for 1 & 2 byte cmpxchg() using read-modify-write atop a 4 byte cmpxchg(). This allows us to support these atomic operations despite the MIPS ISA only providing 4 & 8 byte atomic operations. This is required in order to support queued rwlocks (qrwlock) in a later patch, since these make use of a 1 byte cmpxchg() in their slow path. Signed-off-by:
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Paul Burton authored
Implement 1 & 2 byte xchg() using read-modify-write atop a 4 byte cmpxchg(). This allows us to support these atomic operations despite the MIPS ISA only providing for 4 & 8 byte atomic operations. This is required in order to support queued spinlocks (qspinlock) in a later patch, since these make use of a 2 byte xchg() in their slow path. Signed-off-by:
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Paul Burton authored
Replace the macro definition of __cmpxchg() with an inline function, which is easier to read & modify. The cmpxchg() & cmpxchg_local() macros are adjusted to call the new __cmpxchg() function. Signed-off-by:
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Paul Burton authored
The __xchg_u32() & __xchg_u64() functions now add very little value. This patch therefore removes them, by: - Moving memory barriers out of them & into xchg(), which also removes the duplication & readies us to support xchg_relaxed() if we wish to. - Calling __xchg_asm() directly from __xchg(). - Performing the check for CONFIG_64BIT being enabled in the size=8 case of __xchg(). Signed-off-by: -
Paul Burton authored
xchg() has up until now simply returned the x parameter in cases where it is called with a pointer to a value of an unsupported size. This will often cause the calling code to hit a failure path, presuming that the value of x differs from the content of the memory pointed at by ptr, but we can do better by producing a compile-time or link-time error such that unsupported calls to xchg() are detectable earlier than runtime. This patch does this in the same was as is already done for cmpxchg(), using a call to a missing function annotated with __compiletime_error(). Signed-off-by:
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Paul Burton authored
Our cmpxchg() implementation relies upon generating a call to a function which doesn't really exist (__cmpxchg_called_with_bad_pointer) to create a link failure in cases where cmpxchg() is called with a pointer to a value of an unsupported size. The __compiletime_error macro can be used to decorate a function such that a call to it generates a compile-time, rather than a link-time, error. This patch uses __compiletime_error to cause bad cmpxchg() calls to error out at compile time rather than link time, allowing errors to occur more quickly & making it easier to spot where the problem comes from. Signed-off-by:
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Paul Burton authored
Use a macro to generate the 32 & 64 bit variants of the backing code for xchg(), much as is already done for cmpxchg(). This removes the duplication that could previously be found in __xchg_u32() & __xchg_u64(). Signed-off-by:
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Paul Burton authored
Prior to this patch the xchg & cmpxchg functions have duplicated code which is for all intents & purposes identical apart from use of a branch-likely instruction in the R10000_LLSC_WAR case & a regular branch instruction in the non-R10000_LLSC_WAR case. This patch removes the duplication, declaring a __scbeqz macro to select the branch instruction suitable for use when checking the result of an sc instruction & making use of it to unify the 2 cases. In __xchg_u{32,64}() this means writing the branch in asm, where it was previously being done in C as a do...while loop for the non-R10000_LLSC_WAR case. As this is a single instruction, and adds consistency with the R10000_LLSC_WAR cases & the cmpxchg() code, this seems worthwhile. Signed-off-by: -
Miodrag Dinic authored
Add handling of missaligned access for DSP load instructions lwx & lhx. Since DSP instructions share SPECIAL3 opcode with other non-DSP instructions, necessary logic was inserted for distinguishing between instructions with SPECIAL3 opcode. For that purpose, the instruction format for DSP instructions is added to arch/mips/include/uapi/asm/inst.h. Signed-off-by:
Miodrag Dinic <miodrag.dinic@imgtec.com> Signed-off-by:
Aleksandar Markovic <aleksandar.markovic@imgtech.com> Cc: James.Hogan@imgtec.com Cc: Paul.Burton@imgtec.com Cc: Raghu.Gandham@imgtec.com Cc: Leonid.Yegoshin@imgtec.com Cc: Douglas.Leung@imgtec.com Cc: Petar.Jovanovic@imgtec.com Cc: Goran.Ferenc@imgtec.com Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16511/Signed-off-by:
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Leonid Yegoshin authored
Disable usage of PREF instruction usage by memcpy for MIPS R6. MIPS R6 redefines PREF instruction with smaller offset than ordinary MIPS. However, the memcpy code uses PREF instruction with offsets bigger than +-256 bytes. Malta kernels already disable usage of PREF for memcpy. This was found during adaptation of MIPS R6 for virtual board used by Android emulator. Signed-off-by:
Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by:
Goran Ferenc <goran.ferenc@imgtec.com> Signed-off-by:
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Miodrag Dinic authored
Add "-modd-spreg" when compiling the kernel for mips32r6 target. This makes sure the kernel builds properly even with toolchains that use "-mno-odd-spreg" by default. This is the case with Android gcc. Prior to this patch, kernel builds using gcc for Android failed with following error messages, if target architecture is set to mips32r6: arch/mips/kernel/r4k_switch.S: Assembler messages: .../r4k_switch.S:210: Error: float register should be even, was 1 .../r4k_switch.S:212: Error: float register should be even, was 3 .../r4k_switch.S:214: Error: float register should be even, was 5 .../r4k_switch.S:216: Error: float register should be even, was 7 .../r4k_switch.S:218: Error: float register should be even, was 9 .../r4k_switch.S:220: Error: float register should be even, was 11 .../r4k_switch.S:222: Error: float register should be even, was 13 .../r4k_switch.S:224: Error: float register should be even, was 15 .../r4k_switch.S:226: Error: float register should be even, was 17 .../r4k_switch.S:228: Error: float register should be even, was 19 .../r4k_switch.S:230: Error: float register should be even, was 21 .../r4k_switch.S:232: Error: float register should be even, was 23 .../r4k_switch.S:234: Error: float register should be even, was 25 .../r4k_switch.S:236: Error: float register should be even, was 27 .../r4k_switch.S:238: Error: float register should be even, was 29 .../r4k_switch.S:240: Error: float register should be even, was 31 make[2]: *** [arch/mips/kernel/r4k_switch.o] Error 1 Signed-off-by:
Aleksandar Markovic <aleksandar.markovic@imgtec.com> Cc: James.Hogan@imgtec.com Cc: Paul.Burton@imgtec.com Cc: Raghu.Gandham@imgtec.com Cc: Leonid.Yegoshin@imgtec.com Cc: Douglas.Leung@imgtec.com Cc: Petar.Jovanovic@imgtec.com Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16509/Signed-off-by:
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Miodrag Dinic authored
Implement support for parsing 'memmap' kernel command line parameter. This patch covers parsing of the following two formats for 'memmap' parameter values: - nn[KMG]@ss[KMG] - nn[KMG]$ss[KMG] ([KMG] = K M or G (kilo, mega, giga)) These two allowed formats for parameter value are already documented in file kernel-parameters.txt in Documentation/admin-guide folder. Some architectures already support them, but Mips did not prior to this patch. Excerpt from Documentation/admin-guide/kernel-parameters.txt: memmap=nn[KMG]@ss[KMG] [KNL] Force usage of a specific region of memory. Region of memory to be used is from ss to ss+nn. memmap=nn[KMG]$ss[KMG] Mark specific memory as reserved. Region of memory to be reserved is from ss to ss+nn. Example: Exclude memory from 0x18690000-0x1869ffff memmap=64K$0x18690000 or memmap=0x10000$0x18690000 There is no need to update this documentation file with respect to this patch. Signed-off-by: -
Huacai Chen authored
Sort enum loongson_cpu_type in a more reasonable manner, this makes the CPU names more clear and extensible. Those already defined enum values are renamed to Legacy_* for compatibility. Signed-off-by:
Huacai Chen <chenhc@lemote.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J . Hill <Steven.Hill@cavium.com> Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16591/Signed-off-by:
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Huacai Chen authored
With this patch we can set irq affinity via procfs, so as to improve network performance. Signed-off-by:
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Huacai Chen authored
IRQ0 (HPET), IRQ1 (Keyboard), IRQ2 (Cascade), IRQ7 (SCI), IRQ8 (RTC) and IRQ12 (Mouse) are handled by core-0 locally. Other PCI IRQs (3, 4, 5, 6, 14, 15) are balanced by all cores from Node-0. This can improve I/O performance significantly. Signed-off-by:
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Huacai Chen authored
Loongson-3 machines may have as many as 4 physical packages. Signed-off-by:
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Huacai Chen authored
Signed-off-by:
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- 28 Jun, 2017 21 commits
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Huacai Chen authored
Loongson-3A R3 is very similar to Loongson-3A R2. All Loongson-3 CPU family: Code-name Brand-name PRId Loongson-3A R1 Loongson-3A1000 0x6305 Loongson-3A R2 Loongson-3A2000 0x6308 Loongson-3A R3 Loongson-3A3000 0x6309 Loongson-3B R1 Loongson-3B1000 0x6306 Loongson-3B R2 Loongson-3B1500 0x6307 Signed-off-by:
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Paul Burton authored
The various interrupt specifiers in the device tree are not in a valid format for the MIPS GIC interrupt controller binding. Where each interrupt should provide 3 values - GIC_LOCAL or GIC_SHARED, the pin number & the type of interrupt - the device tree was only providing the pin number. This causes interrupts for those devices to not be used when a GIC is present. SEAD-3 systems without a GIC are unaffected since the DT fixup code generates interrupt specifiers that are valid for the CPU interrupt controller. Fix this by adding the GIC_SHARED & IRQ_TYPE_LEVEL_HIGH values to each interrupt specifier. Signed-off-by:
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Paul Burton authored
The SEAD-3 board may be configured with or without a MIPS Global Interrupt Controller (GIC). Because of this we have a device tree with a default case of a GIC present, and code to fixup the device tree based upon a configuration register that indicates the presence of the GIC. In order to keep this DT fixup code simple, the interrupt-parent property was specified at the root node of the SEAD-3 DT, allowing the fixup code to simply change this property to the phandle of the CPU interrupt controller if a GIC is not present & affect all interrupt-using devices at once. This however causes a problem if we do have a GIC & the device tree is used as-is, because the interrupt-parent property of the root node applies to the CPU interrupt controller node. This causes a cycle when of_irq_init() attempts to probe interrupt controllers in order and boots fail due to a lack of configured interrupts, with this message printed on the kernel console: [ 0.000000] OF: of_irq_init: children remain, but no parents Fix this by removing the interrupt-parent property from the DT root node & instead setting it for each device which uses interrupts, ensuring that the CPU interrupt controller node has no interrupt-parent & allowing of_irq_init() to identify it as the root interrupt controller. Signed-off-by:
Keng Koh <keng.koh@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16187/Signed-off-by:
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Paul Burton authored
Add an entry to MAINTAINERS for the generic platform code, such that relevant people, starting with myself, can be CC'd on patches. Signed-off-by:
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Paul Burton authored
Drivers for the mc146818 RTC generally check control registers to determine whether a value is encoded as binary or as a binary coded decimal. Setting RTC_ALWAYS_BCD to 1 effectively bypasses these checks and causes drivers to always expect binary coded decimal values, regardless of control register values. This does not seem like a sane default - defaulting to 0 allows the drivers to check control registers to determine encoding type & allows the driver to work generically with both binary & BCD encodings. Set this in mach-generic/mc146818rtc.h such that the generic kernel, or platforms which don't provide a custom mc146818rtc.h, can have an RTC driver which works with both encodings. Signed-off-by:
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Paul Burton authored
Introduce an apply_mips_fdt_fixups() function which can apply fixups to an FDT based upon an array of fixup descriptions. This abstracts that functionality such that legacy board code can apply FDT fixups without requiring lots of duplication. Signed-off-by:
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Paul Burton authored
Name aliases in the SEAD-3 device tree serial0 & serial1, rather than uart0 & uart1. This allows the core serial code to make use of the aliases to ensure that the UARTs are consistently numbered as expected rather than having the numbering depend upon probe order. When translating YAMON-provided serial configuration to a device tree stdout-path property adjust accordingly, such that we continue to reference a valid alias. Signed-off-by:
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Paul Burton authored
YAMON can expose more than 256MB of RAM to Linux on Malta by passing an ememsize environment variable with the full size, but the kernel then needs to be careful to choose the corresponding physical memory regions, avoiding the IO memory window. This is platform dependent, and on Malta it also depends on the memory layout which varies between system controllers. Extend yamon_dt_amend_memory() to generically handle this by taking [e]memsize bytes of memory from an array of memory regions passed in as a new parameter. Board code provides this array as appropriate depending on its own memory map. [paul.burton@imgtec.com: SEAD-3 supports 384MB DDR from 0] Signed-off-by:
James Hogan <james.hogan@imgtec.com> Signed-off-by:
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Paul Burton authored
In preparation for supporting other YAMON-using boards (Malta) & sharing code to translate information from YAMON into device tree properties, pull the code doing so for the kernel command line, system memory & serial configuration out of the SEAD-3 board code. Signed-off-by:
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Paul Burton authored
The SEAD-3 board doesn't & never has configured the GIC frequency. Remove the timer node from the DT in order to avoid attempting to probe the GIC clocksource/clockevent driver which will produce error messages such as these during boot: [ 0.000000] GIC frequency not specified. [ 0.000000] Failed to initialize '/interrupt-controller@1b1c0000/timer': -22 [ 0.000000] clocksource_probe: no matching clocksources found Signed-off-by:
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James Hogan authored
Adjust the atomic loop in the MIPS_ATOMIC_SET operation of the sysmips system call to branch straight back to the linked load rather than jumping via a different subsection (whose purpose remains a mystery to me). Signed-off-by:
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James Hogan authored
EVA linked loads (LLE) and conditional stores (SCE) should be used on EVA kernels for the MIPS_ATOMIC_SET operation of the sysmips system call, or else the atomic set will apply to the kernel view of the virtual address space (potentially unmapped on EVA kernels) rather than the user view (TLB mapped). Signed-off-by:
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James Hogan authored
The MIPS sysmips system call handler may return directly from the MIPS_ATOMIC_SET case (mips_atomic_set()) to syscall_exit. This path restores the static (callee saved) registers, however they won't have been saved on entry to the system call. Use the save_static_function() macro to create a __sys_sysmips wrapper function which saves the static registers before calling sys_sysmips, so that the correct static register state is restored by syscall_exit. Fixes: f1e39a4a ("MIPS: Rewrite sysmips(MIPS_ATOMIC_SET, ...) in C with inline assembler") Signed-off-by:
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James Hogan authored
The inline asm retry check in the MIPS_ATOMIC_SET operation of the sysmips system call has been backwards since commit f1e39a4a ("MIPS: Rewrite sysmips(MIPS_ATOMIC_SET, ...) in C with inline assembler") merged in v2.6.32, resulting in the non R10000_LLSC_WAR case retrying until the operation was inatomic, before returning the new value that was probably just written multiple times instead of the old value. Invert the branch condition to fix that particular issue. Fixes: f1e39a4a ("MIPS: Rewrite sysmips(MIPS_ATOMIC_SET, ...) in C with inline assembler") Signed-off-by:
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Marcin Nowakowski authored
Add a definition of the perf registers for the new I6500 core. Since I6500 has the same event definitions as I6400, re-use the existing i6400 map structures by renaming them to a slightly more generic 'i6x00_***_map'. Signed-off-by:
Marcin Nowakowski <marcin.nowakowski@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16362/Signed-off-by:
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Paul Burton authored
Introduce the I6500 PRID & probe it just the same way as I6400. The MIPS I6500 is the latest in Imagination Technologies' I-Class range of CPUs, with a focus on scalability & heterogeneity. It introduces the notion of multiple clusters to the MIPS Coherent Processing System, allowing for a far higher total number of cores & threads in a system when compared with its predecessors. Clusters don't need to be identical, and may contain differing numbers of cores & IOCUs, or cores with differing properties. This patch alone adds the basic support for booting Linux on an I6500 CPU without support for any of its new functionality, for which support will be introduced in further patches. Signed-off-by:
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Paul Burton authored
Recent CPUs from Imagination Technologies such as the I6400 or P6600 are able to speculatively fetch data from memory into caches. This means that if used in a system with non-coherent DMA they require that caches be invalidated after a device performs DMA, and before the CPU reads the DMA'd data, in order to ensure that stale values weren't speculatively prefetched. Such CPUs also introduced Memory Accessibility Attribute Registers (MAARs) in order to control the regions in which they are allowed to speculate. Thus we can use the presence of MAARs as a good indication that the CPU requires the above cache maintenance. Use the presence of MAARs to determine the result of cpu_needs_post_dma_flush() in the default case, in order to handle these recent CPUs correctly. Note that the return type of cpu_needs_post_dma_flush() is changed to bool, such that it's clearer what's happening when cpu_has_maar is cast to bool for the return value. If this patch were backported to a pre-v4.7 kernel then MIPS_CPU_MAAR was 1ull<<34, so when cast to an int we would incorrectly return 0. It so happens that MIPS_CPU_MAAR is currently 1ull<<30, so when truncated to an int gives a non-zero value anyway, but even so the implicit conversion from long long int to bool makes it clearer to understand what will happen than the implicit conversion from long long int to int would. The bool return type also fits this usage better semantically, so seems like an all-round win. Thanks to Ed for spotting the issue for pre-v4.7 kernels & suggesting the return type change. Signed-off-by:
Bryan O'Donoghue <pure.logic@nexus-software.ie> Tested-by:
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David Daney authored
KProbes of __seccomp_filter() are not very useful without access to the syscall arguments. Do what x86 does, and populate a struct seccomp_data to be passed to __secure_computing(). This allows samples/bpf/tracex5 to extract a sensible trace. Signed-off-by:
David Daney <david.daney@cavium.com> Cc: Alexei Starovoitov <ast@kernel.org> Cc: Daniel Borkmann <daniel@iogearbox.net> Cc: Matt Redfearn <matt.redfearn@imgtec.com> Cc: netdev@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16368/Signed-off-by:
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David Daney authored
Since the eBPF machine has 64-bit registers, we only support this in 64-bit kernels. As of the writing of this commit log test-bpf is showing: test_bpf: Summary: 316 PASSED, 0 FAILED, [308/308 JIT'ed] All current test cases are successfully compiled. Many examples in samples/bpf are usable, specifically tracex5 which uses tail calls works. Signed-off-by:
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David Daney authored
Follow on patches for eBPF JIT require these additional instructions: insn_bgtz, insn_blez, insn_break, insn_ddivu, insn_dmultu, insn_dsbh, insn_dshd, insn_dsllv, insn_dsra32, insn_dsrav, insn_dsrlv, insn_lbu, insn_movn, insn_movz, insn_multu, insn_nor, insn_sb, insn_sh, insn_slti, insn_dinsu, insn_lwu ... so, add them. Sort the insn_* enumeration values alphabetically. Signed-off-by:
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David Daney authored
DSHD was incorrectly classified as being BSHFL, and DSHD was missing altogether. Signed-off-by:
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