1. 01 Jul, 2020 4 commits
  2. 29 Jun, 2020 2 commits
  3. 24 Jun, 2020 2 commits
  4. 23 Jun, 2020 2 commits
  5. 22 Jun, 2020 3 commits
  6. 19 Jun, 2020 20 commits
  7. 18 Jun, 2020 1 commit
  8. 17 Jun, 2020 2 commits
  9. 15 Jun, 2020 4 commits
    • Mark Brown's avatar
      Merge series "Add MSIOF support for R8A7742 SOC" from Lad Prabhakar... · 42fd4f25
      Mark Brown authored
      Merge series "Add MSIOF support for R8A7742 SOC" from Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>:
      
      Hi All,
      
      This patch series adds support for MSIOF on R8A7742 SOC.
      
      Cheers,
      Prabhakar
      
      Lad Prabhakar (2):
        dt-bindings: spi: renesas,sh-msiof: Add r8a7742 support
        ARM: dts: r8a7742: Add MSIOF[0123] support
      
       .../devicetree/bindings/spi/renesas,sh-msiof.yaml  |  1 +
       arch/arm/boot/dts/r8a7742.dtsi                     | 64 ++++++++++++++++++++++
       2 files changed, 65 insertions(+)
      
      --
      2.7.4
      42fd4f25
    • Mark Brown's avatar
      Merge series "spi: bcm63xx: add BMIPS support" from Álvaro Fernández Rojas <noltari@gmail.com>: · 75bc1138
      Mark Brown authored
      BCM63xx SPI and HSSPI controller are present on several BMIPS SoCs (BCM6318,
      BCM6328, BCM6358, BCM6362, BCM6368 and BCM63268).
      
      v2: use devm_reset_control_get_exclusive
      
      Álvaro Fernández Rojas (4):
        spi: bcm63xx-spi: add reset support
        spi: bcm63xx-spi: allow building for BMIPS
        spi: bcm63xx-hsspi: add reset support
        spi: bcm63xx-hsspi: allow building for BMIPS
      
       drivers/spi/Kconfig             |  4 ++--
       drivers/spi/spi-bcm63xx-hsspi.c | 17 +++++++++++++++++
       drivers/spi/spi-bcm63xx.c       | 17 +++++++++++++++++
       3 files changed, 36 insertions(+), 2 deletions(-)
      
      --
      2.27.0
      
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      75bc1138
    • Mark Brown's avatar
      Merge series "Add more configuration and regmap support for spi-altera" from... · 731f1e71
      Mark Brown authored
      Merge series "Add more configuration and regmap support for spi-altera" from Xu Yilun <yilun.xu@intel.com>:
      
      This patchset adds platform_data for spi-altera, to enable more IP
      configurations, and creating specific spi client devices. It also adds
      regmap support, to enable the indirect access to this IP.
      
      We have a PCIE based FPGA platform which integrates this IP to communicate
      with a BMC chip (Intel MAX10) over SPI. The IP is configured as 32bit data
      width. There is also an indirect access interface in FPGA for host to
      access the registers of this IP. This patchset enables this use case.
      
      Matthew Gerlach (1):
        spi: altera: fix size mismatch on 64 bit processors
      
      Xu Yilun (5):
        spi: altera: add 32bit data width transfer support.
        spi: altera: add SPI core parameters support via platform data.
        spi: altera: add platform data for slave information.
        spi: altera: use regmap instead of direct mmio register access
        spi: altera: move driver name string to header file
      
       drivers/spi/Kconfig        |   1 +
       drivers/spi/spi-altera.c   | 161 +++++++++++++++++++++++++++++++++++++--------
       include/linux/spi/altera.h |  37 +++++++++++
       3 files changed, 171 insertions(+), 28 deletions(-)
       create mode 100644 include/linux/spi/altera.h
      
      --
      2.7.4
      731f1e71
    • Tim Harvey's avatar
      spi: spi-cavium-thunderx: flag controller as half duplex · e8510d43
      Tim Harvey authored
      The OcteonTX (TX1/ThunderX) SPI controller does not support full
      duplex transactions. Set the appropriate flag such that the spi
      core will return -EINVAL on such transactions requested by chip
      drivers.
      
      This is an RFC as I need someone from Marvell/Cavium to confirm
      if this driver is used for other silicon that does support
      full duplex transfers (in which case we will need to identify
      that we are running on the ThunderX arch before setting the flag).
      Signed-off-by: default avatarTim Harvey <tharvey@gateworks.com>
      Cc: Robert Richter <rrichter@marvell.com>
      Link: https://lore.kernel.org/r/1590680799-5640-1-git-send-email-tharvey@gateworks.comSigned-off-by: default avatarMark Brown <broonie@kernel.org>
      e8510d43