- 22 Apr, 2024 2 commits
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Dave Airlie authored
Merge tag 'drm-misc-next-2024-04-19' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-next drm-misc-next for v6.10-rc1: UAPI Changes: - Add SIZE_HINTS property for cursor planes. Cross-subsystem Changes: Core Changes: - Document the requirements and expectations of adding new driver-specific properties. - Assorted small fixes to ttm. - More Kconfig fixes. - Add struct drm_edid_product_id and helpers. - Use drm device based logging in more drm functions. - Fixes for drm-panic, and option to test it. - Assorted small fixes and updates to edid. - Add drm_crtc_vblank_crtc and use it in vkms, nouveau. Driver Changes: - Assorted small fixes and improvements to bridge/imx8mp-hdmi-tx, nouveau, ast, qaic, lima, vc4, bridge/anx7625, mipi-dsi. - Add drm panic to simpledrm, mgag200, imx, ast. - Use dev_err_probe in bridge/panel drivers. - Add Innolux G121X1-L03, LG sw43408 panels. - Use struct drm_edid in i915 bios parsing. Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/2dc1b7c6-1743-4ddd-ad42-36f700234fbe@linux.intel.com
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Dave Airlie authored
Merge tag 'amd-drm-next-6.10-2024-04-19' of https://gitlab.freedesktop.org/agd5f/linux into drm-next amd-drm-next-6.10-2024-04-19: amdgpu: - DC resource allocation logic updates - DC IPS fixes - DC YUV fixes - DMCUB fixes - DML2 fixes - Devcoredump updates - USB-C DSC fix - Misc display code cleanups - PSR fixes - MES timeout fix - RAS updates - UAF fix in VA IOCTL - Fix visible VRAM handling during faults - Fix IP discovery handling during PCI rescans - Misc code cleanups - PSP 14 updates - More runtime PM code rework - SMU 14.0.2 support - GPUVM page fault redirection to secondary IH rings for IH 6.x - Suspend/resume fixes - SR-IOV fixes amdkfd: - Fix eviction fence handling - Fix leak in GPU memory allocation failure case - DMABuf import handling fix radeon: - Silence UBSAN warnings related to flexible arrays Signed-off-by:
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- 19 Apr, 2024 18 commits
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Dave Airlie authored
Merge tag 'drm-intel-next-2024-04-17-1' of https://anongit.freedesktop.org/git/drm/drm-intel into drm-next Core Changes (DRM): - Fix documentation of DP tunnel functions (Imre) - DP MST read sideband messaging cap (Jani) - Preparation patches for Adaptive Sync SDP Support for DP (Mitul) Driver Changes: i915 core (non-display): - Documentation improvements (Nirmoy) - Add includes for BUG_ON/BUILD_BUG_ON in i915_memcpy.c (Joonas) - Do not print 'pxp init failed with 0' when it succeed (Jose) - Clean-up, including removal of dead code for unsupported platforms (Lucas) - Adding new DG2 PCI ID (Ravi) {i915,xe} display: - Spelling fix (Colin Ian) - Document CDCLK components (Gustavo) - Lunar Lake display enabling, including cdclk and other refactors (Gustavo, Bala) - BIOS/VBT/opregion related refactor (Jani, Ville, RK) - Save a few bytes of memory using {kstrdup,kfree}_const variant (Christophe) - Digital port related refactor/clean-up (Ville) - Fix 2s boot time regression on DP panel replay init (Animesh) - Remove redundant drm_rect_visible() overlay use (Arthur) - DSC HW state readout fixes (Imre) - Remove duplication on audio enable/disable on SDVO and g4x+ DP (Ville) - Disable AuxCCS framebuffers if built for Xe (Juha-Pekka) - Fix DSI init order (Ville) - DRRS related refactor and fixes (Bhanuprakash) - Fix DSB vblank waits with VRR (Ville) - General improvements on register name and use of REG_BIT (Ville) - Some display power well related improvements (Ville) - FBC changes for better w/a handling (Ville) - Make crtc disable more atomic (Ville) - Fix hwmon locking inversion in sysfs getter (Janusz) - Increase DP idle pattern wait timeout to 2ms (Shekhar) - PSR related fixes and improvents (Jouni) - Start using container_of_const() for some extra const safety (Ville) - Use drm_printer more on display code (Ville) - Fix Jasper Lake boot freeze (Jonathon) - Update Pipe src size check in skl_update_scaler (Ankit) - Enable MST mode for 128b/132b single-stream sideband (Jani) - Pass encoder around more for port/phy checks (Jani) - Some initial work to make display code more independent from i915 (Jani) - Pre-populate the cursor physical dma address (Ville) - Do not bump min backlight brightness to max on enable (Gareth) - Fix MTL supported DP rates - removal of UHBR13.5 (Arun) - Fix the computation for compressed_bpp for DISPLAY < 1 (Ankit) - Bigjoiner modeset sequence redesign and MST support (Ville) - Enable Adaptive Sync SDP Support for DP (Mitul) - Implemnt vblank sycnhronized mbus joining changes (Ville, Stanislav) - HDCP related fixes (Suraj) - Fix i915_display_info debugfs when connectors are not active (Ville) - Clean up on Xe compat layer (Jani) - Add jitter WAs for MST/FEC/DSC links (Imre) - DMC wakelock implementation (Luca) Signed-off-by:
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Lang Yu authored
When page table BOs were evicted but not validated before updating page tables, VM is still in evicting state, amdgpu_vm_update_range returns -EBUSY and restore_process_worker runs into a dead loop. v2: Split the BO validation and page table update into two separate loops in amdgpu_amdkfd_restore_process_bos. (Felix) 1.Validate BOs 2.Validate VM (and DMABuf attachments) 3.Update page tables for the BOs validated above Fixes: 50661eb1 ("drm/amdgpu: Auto-validate DMABuf imports in compute VMs") Signed-off-by:
Lang Yu <Lang.Yu@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Felix Kuehling <felix.kuehling@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Mukul Joshi authored
Free the sync object if the memory allocation fails for any reason. Signed-off-by:
Mukul Joshi <mukul.joshi@amd.com> Reviewed-by:
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Felix Kuehling authored
Handle case that dma_fence_get_rcu_safe returns NULL. If restore work is already scheduled, only update its timer. The same work item cannot be queued twice, so undo the extra queue eviction. Fixes: 9a1c1339 ("drm/amdkfd: Run restore_workers on freezable WQs") Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Tested-by:
Gang BA <Gang.Ba@amd.com> Reviewed-by:
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Zhigang Luo authored
Host will initiate an FLR for all poison consumption. Guest should wait for FLR message to re-init data exchange. Signed-off-by:
Zhigang Luo <Zhigang.Luo@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Lijo Lazar authored
On GFX 9.4.3 SOCs, only 2 SDMA instances need to be available to be considered as a valid AID. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Asad Kamal <asad.kamal@amd.com> Reviewed-by:
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Joshua Ashton authored
Otherwise we can end up with a frame on unsuspend where color management is not applied when userspace has not committed themselves. Fixes re-applying color management on Steam Deck/Gamescope on S3 resume. Signed-off-by:
Joshua Ashton <joshua@froggi.es> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Sunil Khatri authored
Enable redirection of irq for pagefaults for specific clients to avoid overflow without dropping interrupts. So here we redirect the interrupts to another IH ring i.e ring1 where only these interrupts are processed. Signed-off-by:
Sunil Khatri <sunil.khatri@amd.com> Reviewed-by:
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Ahmad Rehman authored
In passthrough environment, the driver triggers the mode-1 reset on reload. The reset causes the core dump collection which is delayed task and prevents driver from unloading until it is completed. Since we do not need to collect data on "reset on reload" case, we can skip core dump collection. v2: Use the same flag to avoid calling amdgpu_reset_reg_dumps as well. Signed-off-by:
Ahmad Rehman <Ahmad.Rehman@amd.com> Reviewed-by:
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Sunil Khatri authored
Enable redirection of irq for pagefaults for specific clients to avoid overflow without dropping interrupts. So here we redirect the interrupts to another IH ring i.e ring1 where only these interrupts are processed. Reviewed-by:
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Sunil Khatri authored
Add offsets, mask and shift macros for IH v6.0 which are needed to configure ring1 client irq redirection. Signed-off-by:
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Hawking Zhang authored
mode-2 reset is the only reliable method that can get GC/SDMA back when poison is consumed. mmhub requires mode-1 reset. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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Sunil Khatri authored
We need IH ring1 for handling the pagefault interrupts which over flow in default ring for specific usecases. Signed-off-by:
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Sunil Khatri authored
We need IH ring1 for handling the pagefault interrupts which are overflowing the default ring for specific usecases. Signed-off-by:
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Sumit Semwal authored
LG SW43408 is 1080x2160@60Hz, 4-lane MIPI-DSI panel, used in some Google Pixel-3 phones. Signed-off-by:
Sumit Semwal <sumit.semwal@linaro.org> [vinod: Add DSC support] Signed-off-by:
Vinod Koul <vkoul@kernel.org> [caleb: cleanup and support turning off the panel] Signed-off-by:
Caleb Connolly <caleb@connolly.tech> [DB: partially rewrote the driver and fixed DSC programming] Reviewed-by:
Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20240408-lg-sw43408-panel-v5-4-4e092da22991@linaro.org
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Dmitry Baryshkov authored
Add the extended version of mipi_dsi_compression_mode(). It provides a way to specify the algorithm and PPS selector. Reviewed-by:
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Dmitry Baryshkov authored
The functions mipi_dsi_compression_mode() and mipi_dsi_picture_parameter_set() return 0-or-error rather than a buffer size. Follow example of other similar MIPI DSI functions and use int return type instead of size_t. Fixes: f4dea1aa ("drm/dsi: add helpers for DSI compression mode and PPS packets") Reviewed-by:
Jessica Zhang <quic_jesszhan@quicinc.com> Signed-off-by:
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Sumit Semwal authored
LG SW43408 is 1080x2160, 4-lane MIPI-DSI panel present on Google Pixel 3 phones. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
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- 18 Apr, 2024 4 commits
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Baruch Siach authored
Use 'supported' instead of 'support'. 'support' makes no sense in this context. Signed-off-by:
Baruch Siach <baruch@tkos.co.il> Link: https://patchwork.freedesktop.org/patch/msgid/505484b83fedebce3c65b10b076b34df075074b6.1713329988.git.baruch@tkos.co.ilSigned-off-by:
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Ville Syrjälä authored
Replace the open coded drm_crtc_vblank_crtc() with the real thing. Cc: Rodrigo Siqueira <rodrigosiqueiramelo@gmail.com> Cc: Melissa Wen <melissa.srw@gmail.com> Cc: "Maíra Canal" <mairacanal@riseup.net> Cc: Haneen Mohammed <hamohammed.sa@gmail.com> Cc: Daniel Vetter <daniel@ffwll.ch> Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240408190611.24914-5-ville.syrjala@linux.intel.comReviewed-by:
Maíra Canal <mcanal@igalia.com>
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Ville Syrjälä authored
Replace the open coded drm_crtc_vblank_crtc() with the real thing. Cc: Karol Herbst <kherbst@redhat.com> Cc: Lyude Paul <lyude@redhat.com> Cc: Danilo Krummrich <dakr@redhat.com> Cc: nouveau@lists.freedesktop.org Signed-off-by:
Lyude Paul <lyude@redhat.com>
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Ville Syrjälä authored
Make life easier by providing a function that hands out the correct drm_vblank_crtc for a given a drm_crtc. Also abstract the lower level internals of the vblank code in a similar fashion. Signed-off-by:
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- 17 Apr, 2024 16 commits
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Marek Vasut authored
G121XCE-L01 is a Color Active Matrix Liquid Crystal Display composed of a TFT LCD panel, a driver circuit, and LED backlight system. The screen format is intended to support the 4:3, 1024(H) x 768(V) screen and either 262k/16.7M colors (RGB 6-bits or 8-bits) with LED backlight driver circuit. All input signals are LVDS interface compatible. Documentation [1] and [2] indicate that G121X1-L03 and G121XCE-L01 are effectively identical panels, use the former as RGB 6-bits variant and add the later as RGB 8-bits variant. [1] https://www.distec.de/fileadmin/pdf/produkte/TFT-Displays/Innolux/G121X1-L03_Datasheet.pdf [2] https://www.distec.de/fileadmin/pdf/produkte/TFT-Displays/Innolux/G121XCE-L01_Datasheet.pdfSigned-off-by:
Marek Vasut <marex@denx.de> Acked-by:
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Marek Vasut authored
Use display_timing instead of drm_display_mode to define a range of possible display timings supported by this panel. This makes the panel support more flexible and improves compatibility. No functional change is expected. The settings are picked from documentation [1] section 6.1 INPUT SIGNAL TIMING SPECIFICATIONS. [1] https://www.distec.de/fileadmin/pdf/produkte/TFT-Displays/Innolux/G121X1-L03_Datasheet.pdfSigned-off-by:
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Marek Vasut authored
The .bpc = 6 implies .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG , add the missing bus_format. Add missing connector type and bus_flags as well. Documentation [1] 1.4 GENERAL SPECIFICATI0NS indicates this panel is capable of both RGB 18bit/24bit panel, the current configuration uses 18bit mode, .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG , .bpc = 6. Support for the 24bit mode would require another entry in panel-simple with .bus_format = MEDIA_BUS_FMT_RGB666_1X7X4_SPWG and .bpc = 8, which is out of scope of this fix. [1] https://www.distec.de/fileadmin/pdf/produkte/TFT-Displays/Innolux/G121X1-L03_Datasheet.pdf Fixes: f8fa17ba ("drm/panel: simple: Add support for Innolux G121X1-L03") Signed-off-by:
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Marek Vasut authored
Document support for Innolux CheMei 12" G121XCE-L01 XGA LVDS display. G121XCE-L01 is a Color Active Matrix Liquid Crystal Display composed of a TFT LCD panel, a driver circuit, and LED backlight system. The screen format is intended to support the 4:3, 1024(H) x 768(V) screen and either 262k/16.7M colors (RGB 6-bits or 8-bits) with LED backlight driver circuit. All input signals are LVDS interface compatible. Documentation [1] and [2] indicate that G121X1-L03 and G121XCE-L01 are effectively identical panels, use the former as RGB 6-bits variant and document the later as RGB 8-bits variant. [1] https://www.distec.de/fileadmin/pdf/produkte/TFT-Displays/Innolux/G121X1-L03_Datasheet.pdf [2] https://www.distec.de/fileadmin/pdf/produkte/TFT-Displays/Innolux/G121XCE-L01_Datasheet.pdfSigned-off-by:
Conor Dooley <conor.dooley@microchip.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240328102746.17868-1-marex@denx.de
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Jani Nikula authored
Repurpose drm_edid_are_equal() to be more helpful for its single user, and rename drm_edid_eq(). Functionally deduce the length from the blob size, not the blob data, making it more robust against any errors. Reviewed-by:
Thomas Zimmermann <tzimmermann@suse.de> Link: https://patchwork.freedesktop.org/patch/msgid/1011a285d30babce3aabd8218abb7ece7dcf58a2.1713259151.git.jani.nikula@intel.comSigned-off-by:
Jani Nikula <jani.nikula@intel.com>
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Jani Nikula authored
drm_edid_are_equal() is only used within drm_edid.c. Make it static. Do not encourage more uses of struct edid. Reviewed-by:
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Jani Nikula authored
Prefer the EDID iterators over drm_edid_find_extension() in drm_edid_has_cta_extension(), even if this leads to more code. The key is to use the same patterns as much as possible. Reviewed-by:
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Jani Nikula authored
Follow the drm_edid_ naming convention. Reviewed-by:
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Jani Nikula authored
Keep the declarations for struct drm_edid based functions together. Reviewed-by:
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Jani Nikula authored
The declarations for internal EDID functions are a bit scattered. Put them all in drm_crtc_internal.h. Reviewed-by:
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Jani Nikula authored
There are no exported symbols for displayid, and it's all internal interfaces. Move the header to drivers/gpu/drm/drm_displayd_internal.h. Reviewed-by:
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Luca Coelho authored
We only need DMC wakelocks when we allow DC5 and DC6 states. Add the calls to enable and disable DMC wakelock accordingly. Reviewed-by:
Uma Shankar <uma.shankar@intel.com> Signed-off-by:
Luca Coelho <luciano.coelho@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240412094148.808179-5-luciano.coelho@intel.comSigned-off-by:
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Luca Coelho authored
This feature should be disabled by default until properly tested and mature. Add a module parameter to enable the feature for testing, while keeping it disabled by default for now. Reviewed-by:
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Luca Coelho authored
Only allow running DMC wakelock code if the display version is 20 or greater. Also check if DMC is loaded before enabling. Reviewed-by:
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Luca Coelho authored
In order to reduce the DC5->DC2 restore time, wakelocks have been introduced in DMC so the driver can tell it when registers and other memory areas are going to be accessed and keep their respective blocks awake. Implement this in the driver by adding the concept of DMC wakelocks. When the driver needs to access memory which lies inside pre-defined ranges, it will tell DMC to set the wakelock, access the memory, then wait for a while and clear the wakelock. The wakelock state is protected in the driver with spinlocks to prevent concurrency issues. BSpec: 71583 Signed-off-by:
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Dave Airlie authored
Merge tag 'amd-drm-next-6.10-2024-04-13' of https://gitlab.freedesktop.org/agd5f/linux into drm-next amd-drm-next-6.10-2024-04-13: amdgpu: - HDCP fixes - ODM fixes - RAS fixes - Devcoredump improvements - Misc code cleanups - Expose VCN activity via sysfs - SMY 13.0.x updates - Enable fast updates on DCN 3.1.4 - Add dclk and vclk reporting on additional devices - Add ACA RAS infrastructure - Implement TLB flush fence - EEPROM handling fixes - SMUIO 14.0.2 support - SMU 14.0.1 Updates - Sync page table freeing with TLB flushes - DML2 refactor - DC debug improvements - SR-IOV fixes - Suspend and Resume fixes - DCN 3.5.x Updates - Z8 fixes - UMSCH fixes - GPU reset fixes - HDP fix for second GFX pipe on GC 10.x - Enable secondary GFX pipe on GC 10.3 - Refactor and clean up BACO/BOCO/BAMACO handling - VCN partitioning fix - DC DWB fixes - VSC SDP fixes - DCN 3.1.6 fix - GC 11.5 fixes - Remove invalid TTM resource start check - DCN 1.0 fixes amdkfd: - MQD handling cleanup - Preemption handling fixes for XCDs - TLB flush fix for GC 9.4.2 - Properly clean up workqueue during module unload - Fix memory leak process create failure - Range check CP bad op exception targets to avoid reporting invalid exceptions to userspace radeon: - Misc code cleanups From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240413213708.3427038-1-alexander.deucher@amd.comSigned-off-by:
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