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- 17 Jun, 2013 3 commits
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Shawn Guo authored
There is a redundant ocotp node. Remove it. Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Shawn Guo authored
There is a redundant label on usbmisc node. Remove it. Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Dirk Behme authored
Configure the data and tag latency for the L2 cache. This improves the system performance. This configuration is taken from Freescale's kernel patch "ENGR00153601 [MX6]Adjust L2 cache parameter" [1] which does writel(0x132, IO_ADDRESS(L2_BASE_ADDR + L2X0_TAG_LATENCY_CTRL)); writel(0x132, IO_ADDRESS(L2_BASE_ADDR + L2X0_DATA_LATENCY_CTRL)); In this patch we are doing the same via the device tree. Signed-off-by:
Dirk Behme <dirk.behme@de.bosch.com> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org> [1] http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/arch/arm/mach-mx6/mm.c?h=imx_3.0.35_12.09.01&id=814656410b40c67a10b25300e51b0477b2bb96d1
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- 09 Apr, 2013 7 commits
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Philipp Zabel authored
The SRC in i.MX51 and i.MX53 is similar to the one in i.MX6q minus the IPU2 reset line and multi core CPU reset/enable bits. Signed-off-by:
Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by:
Stephen Warren <swarren@nvidia.com> Reviewed-by:
Marek Vasut <marex@denx.de> Reviewed-by:
Pavel Machek <pavel@ucw.cz> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Philipp Zabel authored
Signed-off-by:
Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by:
Stephen Warren <swarren@nvidia.com> Reviewed-by:
Marek Vasut <marex@denx.de> Reviewed-by:
Pavel Machek <pavel@ucw.cz> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Steffen Trumtrar authored
Add ldb device tree node and clock lookups. Signed-off-by:
Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by:
Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Sascha Hauer authored
The i.MX6 already has a devicetree node for the GPT, but not yet has the clocks. Add them. Signed-off-by:
Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Shawn Guo authored
Replace /include/ (dtc) with #include (C pre-processor) for all imx DT files, so that gcc -E handles the entire include tree, and hence any of those files can #include some other file e.g. for constant definitions. This allows future use of #defines and header files in order to define names for various constants, such as pinctrl settings. Use of those features will increase the readability of the device tree files. Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Dirk Behme authored
Add ARM Cortex A9 Performance Monitor Unit (PMU) support. On i.MX6 a combined interrupt on hardware line #126 is used (i.MX6 TRM: Performance Unit interrupt). For more details see Documentation/devicetree/bindings/arm/pmu.txt Signed-off-by:
Dirk Behme <dirk.behme@de.bosch.com> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Shawn Guo authored
While booting from device tree, imx6q used to provide twd clock lookup by calling clk_register_clkdev() in clock driver. However, the commit bd603455 (ARM: use device tree to get smp_twd clock) forces DT boot to look up the clock from device tree. It causes the failure below when twd driver tries to get the clock, and hence kernel has to calibrate the local timer frequency. smp_twd: clock not found -2 ... Calibrating local timer... 396.13MHz. Fix the regression by providing twd clock lookup from device tree, and remove the unused twd clk_register_clkdev() call from clock driver. Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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- 04 Apr, 2013 1 commit
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Shawn Guo authored
Add generic DMA device tree binding for mxs-dma. The changes include: * Add channel interrupts into DMA controller nodes * Add properties '#dma-cells' and 'dma-channels' for DMA controller nodes * And properties 'dmas' and 'dma-names' for DMA client nodes * Update mxs-dma device tree binding doc Signed-off-by:
Shawn Guo <shawn.guo@linaro.org> Reviewed-by:
Arnd Bergmann <arnd@arndb.de>
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- 10 Feb, 2013 6 commits
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Shawn Guo authored
Add dtsi for imx6q and imx6dl with non-common blocks moved into there. Major differences between imx6dl and imx6q: * Dual vs. Quad cores * single vs. dual IPU * 128 vs. 256 KB OCRAM * imx6q: ECSPI5, OpenVG (GC355), SATA * imx6dl: I2C4, PXP, EPDC, LCDIF * iomuxc/pads definition Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Shawn Guo authored
i.MX6 Quad and i.MX6 DualLite is similar enough to share one dtsi file, so rename imx6q.dtsi to imx6qdl.dtsi preparing for the addition of imx6dl support. Another member of i.MX6 series i.MX6 SoloLite is different enough from the other two, so it will stand as a separate dtsi. That's why we rename to imx6qdl.dtsi not imx6.dtsi. Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Anson Huang authored
For ANATOP LDOs, vddcpu, vddsoc and vddpu have step time settings in the misc2 register, need to add necessary step time info for these three LDOs, then regulator driver can add necessary delay based on these settings. offset 0x170: bit [24-25]: vddcpu bit [26-27]: vddpu bit [28-29]: vddsoc field definition: 0'b00: 64 cycles of 24M clock; 0'b01: 128 cycles of 24M clock; 0'b02: 256 cycles of 24M clock; 0'b03: 512 cycles of 24M clock; Signed-off-by:
Anson Huang <b20788@freescale.com> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Shawn Guo authored
Update operating-points per hardware document and add support for 1 GHz and 1.2 GHz frequencies. 400 MHz, 800 MHz and 1 GHz should be supported by all i.MX6Q chips, while 1.2 GHz support needs to know from OTP fuse bit. Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Fabio Estevam authored
Remove silicon version from SDMA firmware. This makes it consistent with other i.MX SoCs firmware names. Signed-off-by:
Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Shawn Guo authored
Following omap3-evm.dts way, it changes all imx dts files to use label in board dts to refer to nodes defined by soc dtsi. Thus, the board dts files become easier to read and edit with the least indentation levels. Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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- 05 Feb, 2013 1 commit
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Frank Li authored
ptp should use enet_ref instead of pll6_enet pll6_enet is fixed 500Mhz. There are divider between enet_ref and pll6_enet Signed-off-by:
Frank Li <Frank.Li@freescale.com> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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- 22 Nov, 2012 1 commit
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Sascha Hauer authored
Signed-off-by:
Sascha Hauer <s.hauer@pengutronix.de> Acked-by:
Shawn Guo <shawn.guo@linaro.org>
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- 16 Nov, 2012 5 commits
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Sascha Hauer authored
This adds the IPU devices to the devicetree. Signed-off-by:
Sascha Hauer <s.hauer@pengutronix.de> Acked-by:
Shawn Guo <shawn.guo@linaro.org>
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Sascha Hauer authored
Having labels before each node allows board bindings to reference to nodes by using the &nodename {} notation. This way boards do not have to resemble the whole devicetree layout. Due to less indention needed the board files also get better readability. Since the label make the documentation behind the nodes unnecessary it is removed. Signed-off-by:
Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Shawn Guo authored
It enables cpufreq support for imx6q with generic cpufreq-cpu0 driver. Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Shawn Guo authored
Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Sascha Hauer authored
According to Documentation/devicetree/bindings/mmc/mmc.txt bus-width is a mandatory property. While this is currently enforced nowhere, it's a good habit to just add the property now to allow to add common helper functionality for the mmc property parsing later. Signed-off-by:
Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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- 01 Nov, 2012 1 commit
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Frank Li authored
Add ENET 1588 clock input pin MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT and anatop PLL8 clock source for ENET Signed-off-by:
Frank Li <Frank.Li@freescale.com> Signed-off-by:
David S. Miller <davem@davemloft.net>
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- 15 Oct, 2012 1 commit
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Shawn Guo authored
This is some amount of work left/forgot from device tree conversion. Instead of checking cpu_is_xxx to determine the controller type, the driver should use platform_device_id, which should match the device tree compatible string. The patch changes the driver to use platform_device_id rather than cpu_is_xxx to determine the controller type/version. It also updates the platform code and device tree source accordingly. As the result, mach/hardware.h inclusion gets removed from the driver. Signed-off-by:
Shawn Guo <shawn.guo@linaro.org> Acked-by:
Sascha Hauer <s.hauer@pengutronix.de> Acked-by:
Arnd Bergmann <arnd@arndb.de> Cc: Wolfram Sang <w.sang@pengutronix.de> Cc: linux-i2c@vger.kernel.org
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- 19 Sep, 2012 1 commit
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Richard Zhao authored
Signed-off-by:
Richard Zhao <richard.zhao@freescale.com> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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- 17 Sep, 2012 3 commits
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Dong Aisheng authored
Using syscon to access anatop register. Acked-by:
Mark Brown <broonie@opensource.wolfsonmicro.com> Acked-by:
Stephen Warren <swarren@wwwdotorg.org> Signed-off-by:
Dong Aisheng <dong.aisheng@linaro.org> Signed-off-by:
Samuel Ortiz <sameo@linux.intel.com>
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Dong Aisheng authored
Include headfile for easy using. Acked-by:
Stephen Warren <swarren@wwwdotorg.org> Signed-off-by:
Dong Aisheng <dong.aisheng@linaro.org> Signed-off-by:
Samuel Ortiz <sameo@linux.intel.com>
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Richard Zhao authored
- add usbmisc device - set property fsl,usbmisc for usb controllers - set disable-over-current for imx6q-sabrelite usb otg Signed-off-by:
Richard Zhao <richard.zhao@freescale.com> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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- 11 Sep, 2012 7 commits
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Shawn Guo authored
It really becomes an maintenance issue that every time a device needs to look up (clk_get) a clock we have to patch kernel clock file to call clk_register_clkdev for that clock. Since clock DT support which is meant to resolve clock lookup in device tree is in place, the patch moves imx6q client devices' clock lookup over to device tree, so that any new lookup to be added at later time can just get done in DT instead of kernel. Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Shawn Guo authored
Add pinctrl settings for existing devices in imx6q-sabresd.dts. Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Shawn Guo authored
Add missing pinctrl of uart and enet for imx6q-arm2 board. Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Shawn Guo authored
Add missing pinctrl of usdhc and enet for imx6q-sabrelite board. Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Shawn Guo authored
Sort iomuxc sub-nodes in name so that the node can be located a little bit easier. Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Shawn Guo authored
Name iomuxc sub-nodes following pin function and hardware manual. Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Shawn Guo authored
Change the indentation for property fsl,pins a little bit, so that the first and the last line get the same indentation with all other lines. Then it will be easier to copy and past any of these lines. Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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- 24 Aug, 2012 1 commit
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Fabio Estevam authored
Instead of enabling the watchdog in each individual dts file, select in the SoC dtsi file instead. Signed-off-by:
Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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- 07 Aug, 2012 1 commit
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Shawn Guo authored
Add alias for gpio nodes, so that gpio driver can identify the port number and then specify a sensible gpio base rather than using the one dynamically allocated by gpio core. Signed-off-by:
Shawn Guo <shawn.guo@linaro.org> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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- 17 Jul, 2012 1 commit
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Benoît Thébaudeau authored
Some mxc processors have an edge_sel feature, which allows the IRQ to be triggered by any edge. This patch makes use of this feature if available, which skips mxc_flip_edge(). Cc: Grant Likely <grant.likely@secretlab.ca> Cc: Linus Walleij <linus.walleij@stericsson.com> Acked-by:
Sascha Hauer <kernel@pengutronix.de> Cc: <linux-arm-kernel@lists.infradead.org> Signed-off-by:
Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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