- 21 Jun, 2022 40 commits
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Rodrigo Siqueira authored
We already have DALSMC_MSG_TransferTableDram2Smu in the file dalsmc.h; for this reason, we don't need this definition in the smu msg file. Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Rodrigo Siqueira authored
In DCN32 clk hook functions, we are using the wrong reference for get_dp_ref_clk_frequency and missing the get_dtb_ref_clk_frequency reference. This commit adds those references. Tested-by:
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Chaitanya Dhere authored
[Why] For DCN32 we do not have a pme workaround function defined that sends a BacoAudio message. Default code had uses the DCN30 function for pme workaround. PMFW headers are inconsistent with their message ID definitions which cause ID's to clash leading to inconsistent system behaviour. There is a clash with FCLK message due to inconsitent PMFW headers. [How] Implement a new BacoAudio function to workaround the problem of inconsistent PMFW headers in order to avoid BacoAudio message clasing with FCLK Enable message. Tested-by:
Chaitanya Dhere <chaitanya.dhere@amd.com> Signed-off-by:
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Rodrigo Siqueira authored
Add support to get VCO frequency from registers. Tested-by:
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Alvin Lee authored
FCLK not supported for DCN321, but still need to update the software state accordingly to prevent unneeded full updates in driver Tested-by:
Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by:
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George Shen authored
[Why] Certain use cases will pass in zero in the new_clocks parameter for all clocks. This results in a divide-by-zero error when attempting to round up the new clock. When new_clocks are zero, no rounding is required, so we can skip it. [How] Guard the division calculation with a check to make sure clocks are not zero. Tested-by:
George Shen <george.shen@amd.com> Signed-off-by:
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Alvin Lee authored
[Description] - When lowering DPPCLK, we want to program the DPP DTO before updating the DPP refclk. - Also update DPPCLK to the exact frequency that will be set after clock divider has been programmed. This will prevent rounding errors when making the request to PMFW (we need DPP DTO to match exactly with the exact DPP refclk). Tested-by:
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Rodrigo Siqueira authored
Our debug struct has the min_disp_clk_khz and min_dpp_clk_khz options, which we ignore in the DCN32. This commit introduces those checks and the necessary calculation. Tested-by:
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Dmytro Laktyushkin authored
[Why & How] Check if aux is not accessible before updating payload allocation table. Tested-by:
Alan Liu <HaoPing.Liu@amd.com> Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Signed-off-by:
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Wenjing Liu authored
[Why & How] Extract update stream allocation table into link hwss as part of the link hwss refactor work. Tested-by:
Wenjing Liu <wenjing.liu@amd.com> Signed-off-by:
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George Shen authored
[Why & How] Old vendor specific w/a are no longer needed and unused. Clean up codebase by removing them. Tested-by:
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George Shen authored
[Why] Several issues were discovered that caused link training to fail when an LTTPR device is connected downstream for the fixed VS sequence. [How] The following were added: - workaround to configure AUX timeout for fixed VS sequence - additional delay before disabling fixed VS intercept - detection of fixed VS deadlock state and performing DPCD sequence to recover Tested-by:
Meenakshikumar Somasundaram <Meenakshikumar.Somasundaram@amd.com> Acked-by:
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George Shen authored
[Why] The function currently skips overriding the drive settings of the first lane. [How] Change for loop to start at 0 instead of 1. Tested-by:
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Aric Cyr authored
[Why & How] Change struct initializer from multiple brace to single brace. Tested-by:
Aric Cyr <aric.cyr@amd.com> Signed-off-by:
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Wenjing Liu authored
[why] This is one of the major steps to decouple hw lane settings from dpcd lane settings. Tested-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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George Shen authored
[Why & How] Check always_match_dpcd_with_hw_lane_settings bit before overriding the DP drive settings Tested-by:
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Wenjing Liu authored
[Why & How] Enrich the log to provide more informatio in MST payload update. Tested-by:
Ariel Bernstein <Eric.Bernstein@amd.com> Acked-by:
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JinZe.Xu authored
[Why & How] Use dc_is_hdmi_signal to determine signal type. Tested-by:
JinZe.Xu <JinZe.Xu@amd.com> Signed-off-by:
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Qingqing Zhuo authored
[Why] Wrong index was checked for dcfclk_mhz, causing false warning. [How] Fix the assertion index. Tested-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by:
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Saaem Rizvi authored
[WHY] Logging for SMU response value after the wait allows us to know immediately what the response value was. Makes it easier to debug should the value be anything other than OK. [HOW] Using the the already available DC SMU logging functions. Tested-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
Saaem Rizvi <SyedSaaem.Rizvi@amd.com> Signed-off-by:
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Sung Joon Kim authored
[why] For VG, we want to turn off power/backlight of the intenral panel when plugging in external monitor and going to "external monitor only" mode. [how] For turning off power of the internal panel, ignore the config flag whic bypasses power sequencing for eDP panels. Tested-by:
Sung Joon Kim <sungkim@amd.com> Signed-off-by:
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Sung Joon Kim authored
[why] Only on VG, if external display is disconnected during S3 suspend, the internal panel doesn't light up on resume because we set the power state using an unsupported DPCD register SET_POWER. To check the register is supported, we need to check SET_POWER_CAPABLE first which is eDP-specific DPCD register field. [how] Check the SET_POWER_CAPABLE register field and decide the control of the eDP power state based on the read register value. Tested-by:
Agustin Gutierrez <Agustin.Gutierrez@amd.com> Acked-by:
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hersen wu authored
[Why] when connect one 4k@144hz dp to dsc mst hub, 4k@144hz mode is in valid mode list. but some mst hub port output bandwidth does not support 4k@144hz. [How] add mst port output bandwidth checks, include full_pbn, branch max throughput mps. Tested-by:
Jerry Zuo <Jerry.Zuo@amd.com> Acked-by:
hersen wu <hersenxs.wu@amd.com> Signed-off-by:
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Ian Chen authored
Delete unnecessary codes in detect_link_and_local_sink. We already have correct stop logic in dc_link_detect. Tested-by:
Ian Chen <ian.chen@amd.com> Signed-off-by:
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Wayne Lin authored
[Why] While updating the config of hdcp, we use the sink_singal type of the dc_sink to decide the HDCP operation mode. However, it doesn't consider the case when the sink is a emulated one. [How] Take dc_em_sink into account while updating HDCP config. Tested-by:
Wayne Lin <Wayne.Lin@amd.com> Signed-off-by:
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Wayne Lin authored
[Why] Observe that we have several problems while releasing remote dc_sink under mst cases. - When unplug mst branch device from the source, we now try to free all remote dc_sinks in dm_helpers_dp_mst_stop_top_mgr(). However, there are bugs while we're releasing dc_sinks here. First of all, link->remote_sinks[] array get shuffled within dc_link_remove_remote_sink(). As the result, increasing the array index within the releasing loop is wrong. Secondly, it tries to call dc_sink_release() to release the dc_sink of the same aconnector every time in the loop. Which can't release dc_sink of all aconnector in the mst topology. - There is no code path for us to release remote dc_sink for disconnected sst monitor which unplug event is notified by CSN sideband message. Which means we'll use stale dc_sink data to represent later on connected monitor. Also, has chance to break the maximum remote dc_sink number constraint. [How] Distinguish unplug event of mst scenario into 2 cases. * Unplug sst/legacy stream sink off the mst topology - Release related remote dc_sink in detec_ctx(). * Unplug mst branch device off the mst topology - Release related remote dc_sink in early_unregister() Tested-by:
Lyude Paul <lyude@redhat.com> Signed-off-by:
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Wayne Lin authored
This reverts commit 3c4d55c9. Revert the commit because: - It's incomplete of the function dm_set_dpms_off() for mst case. For stream sinks whithin the same mst topology, they share the same dc_link. dm_set_dpms_off() tries to update one mst stream only which is incomplete. - Setting dpms off should be triggered by usermode. Besdies, it seems usermode does release relevant resource for mst & non-mst case when unplug connecotr now. Tested-by:
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Wayne Lin authored
This reverts commit 035f5496. The reverted commit was trying to fix side effect brought by commit 3c4d55c9 ("drm/amd/display: turn DPMS off on connector unplug") However, * This reverted commit will have mst case never call dm_set_dpms_off() which conflicts the idea of original commit 3c4d55c9 ("drm/amd/display: turn DPMS off on connector unplug") That's due to dm_crtc_state is always null since the input parameter aconnector is the root device (source) of mst topology. It's not an end stream sink within the mst topology. * Setting dpms off should be triggered by usermode. Besdies, it seems usermode does release relevant resource for mst & non-mst case when unplug connecotr now. Which means we no longer need both commits now: commit 3c4d55c9 ("drm/amd/display: turn DPMS off on connector unplug") commit 035f5496 ("drm/amd/display: Add flag to detect dpms force off during HPD") Tested-by:
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Mario Limonciello authored
A variety of Lenovo machines with Rembrandt APUs and OLED panels have stopped showing the display at login. This behavior clears up after leaving it idle and moving the mouse or touching keyboard. It was bisected to be caused by commit 559e2655 ("drm/amd/display: keep eDP Vdd on when eDP stream is already enabled"). Revert this commit to fix the issue. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2047Reported-by:
Aaron Ma <aaron.ma@canonical.com> Fixes: 559e2655 ("drm/amd/display: keep eDP Vdd on when eDP stream is already enabled") Signed-off-by:
Mario Limonciello <mario.limonciello@amd.com> Tested-by:
Mark Pearson <markpearson@lenovo.com> Acked-by:
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Cruise Hung authored
Tested-by:
Cruise Hung <Cruise.Hung@amd.com> Signed-off-by:
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Yifan Zhang authored
This patch adds LSDMA ip block for LSDMA v6.0.1. Signed-off-by:
Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by:
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Aurabindo Pillai authored
[Why&How] The omitted register definition caused call traces like: [ 3.811215] WARNING: CPU: 7 PID: 794 at drivers/gpu/drm/amd/amdgpu/../display/dc/dc_helper.c:120 set_reg_field_values.constprop.0+0xc7/0xe0 [amdgpu] [ 3.811406] Modules linked in: amdgpu(+) drm_ttm_helper ttm iommu_v2 gpu_sched drm_kms_helper cfbfillrect syscopyarea cfbimgblt sysfillrect sysimgblt fb_sys_fops cfbcopyarea drm i2c_piix4 drm_panel_orientation_quirks [ 3.811419] CPU: 7 PID: 794 Comm: systemd-udevd Not tainted 5.16.0-kfd+ #132 [ 3.811422] Hardware name: System manufacturer System Product Name/ROG STRIX B450-F GAMING, BIOS 3003 12/09/2019 [ 3.811425] RIP: 0010:set_reg_field_values.constprop.0+0xc7/0xe0 [amdgpu] [ 3.811615] Code: 08 49 89 51 08 8b 08 48 8d 42 08 49 89 41 08 44 8b 02 48 8d 50 08 0f b6 c9 49 89 51 08 8b 00 45 85 c0 75 b3 0f 0b eb af 5d c3 <0f> 0b e9 48 ff ff ff 49 8b 51 08 eb d0 49 8b 41 08 eb d5 66 0f 1f [ 3.811619] RSP: 0018:ffffb8c1c04cf640 EFLAGS: 00010246 [ 3.811621] RAX: 0000000000000000 RBX: ffff96f2100d8800 RCX: 0000000000000000 [ 3.811623] RDX: 0000000000000000 RSI: 0000000000000001 RDI: ffffb8c1c04cf650 [ 3.811625] RBP: ffffb8c1c04cf640 R08: 000000000000047f R09: ffffb8c1c04cf658 [ 3.811627] R10: ffff96f5161ff000 R11: ffff96f5161ff000 R12: ffff96f204afb9c0 [ 3.811629] R13: 0000000000000000 R14: ffff96f202b94c00 R15: ffffb8c1c04cf718 [ 3.811631] FS: 00007fe07c2e2880(0000) GS:ffff96f5059c0000(0000) knlGS:0000000000000000 [ 3.811634] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 3.811636] CR2: 0000559634ab57b8 CR3: 0000000120674000 CR4: 00000000003506e0 [ 3.811637] Call Trace: [ 3.811640] <TASK> [ 3.811642] generic_reg_update_ex+0x69/0x200 [amdgpu] [ 3.811831] ? _printk+0x58/0x6f [ 3.811836] dcn32_init_crb+0x18f/0x1b0 [amdgpu] [ 3.812031] dcn32_init_hw+0x379/0x6a0 [amdgpu] [ 3.812223] dc_hardware_init+0xba/0x100 [amdgpu] [ 3.812415] amdgpu_dm_init.isra.0.cold+0x166/0x1867 [amdgpu] [ 3.812616] ? dev_vprintk_emit+0x139/0x15d [ 3.812621] ? dev_printk_emit+0x4e/0x65 [ 3.812624] dm_hw_init+0x12/0x30 [amdgpu] [ 3.812820] amdgpu_device_init.cold+0x130d/0x178c [amdgpu] [ 3.813017] ? pci_read_config_word+0x25/0x40 [ 3.813021] amdgpu_driver_load_kms+0x1a/0x130 [amdgpu] [ 3.813178] amdgpu_pci_probe+0x130/0x330 [amdgpu] Fixes: 4f29f9cf ("drm/amd: add register headers for DCN32/321") Signed-off-by:
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Mario Limonciello authored
Some APUs with SMU13 are showing the following message: `amdgpu 0000:63:00.0: amdgpu: Unexpected and unhandled version: 3.1` This warning isn't relevant for smu info 3.1, as no bootup information is present in the table. Fixes: 593a54f1 ("drm/amd/pm: correct the way for retrieving bootup clocks") Signed-off-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Yang Wang authored
set mp1 unload state will cause the SMC FW can't accept any SMU message, skip to set mp1 unload state to avoid following case fail: - runtime pm case. - gpu reset case. Fixes: 72aeb6ee ("drm/amd/pm: fix driver reload SMC firmware fail issue for smu13") Signed-off-by:
Yang Wang <KevinYang.Wang@amd.com> Reviewed-by:
Kenneth Feng <kenneth.feng@amd.com> Signed-off-by:
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Jack Xiao authored
Due to gfxoff on, cpu accessing registers is not expected. Signed-off-by:
Jack Xiao <Jack.Xiao@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Stanley.Yang authored
The EccInfo_t struct in driver_if.h is as below in official release verion 68.55.0 typedef struct { uint64_t mca_umc_status; uint64_t mca_umc_addr; uint16_t ce_count_lo_chip; uint16_t ce_count_hi_chip; uint32_t eccPadding; uint64_t mca_ceumc_addr; } EccInfo_t; It's different from the debug version druing develop print correctable error address, so adjust EccInfo_t struct. Signed-off-by:Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by:
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Alex Deucher authored
Certain GL unit tests for large textures can cause problems with the OOM killer since there is no way to link this memory to a process. This was originally mitigated (but not necessarily eliminated) by limiting the GTT size. The problem is this limit is often too low for many modern games so just make the limit 1/2 of system memory. The OOM accounting needs to be addressed, but we shouldn't prevent common 3D applications from being usable just to potentially mitigate that corner case. Set default GTT size to max(3G, 1/2 of system ram) by default. v2: drop previous logic and default to 3/4 of ram v3: default to half of ram to align with ttm v4: fix spelling in comment (Kent) Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1942Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Signed-off-by:
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Alex Deucher authored
radeon is MIT. This were incorrectly changed in commit b2441318 ("License cleanup: add SPDX GPL-2.0 license identifier to files with no license") and commit d198b34f (".gitignore: add SPDX License Identifier") and: commit ec8f24b7 ("treewide: Add SPDX license identifier - Makefile/Kconfig") Fixes: d198b34f (".gitignore: add SPDX License Identifier") Fixes: ec8f24b7 ("treewide: Add SPDX license identifier - Makefile/Kconfig") Fixes: b2441318 ("License cleanup: add SPDX GPL-2.0 license identifier to files with no license") Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2053Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Graham Sider authored
Loop through all VMIDs for gmc_v10_0_flush_gpu_tlb_pasid and gmc_v11_0_flush_gpu_tlb_pasid (only if using MES for gmc_v10). This is required for MES due to use_different_vmid_compute causing SDMA queues to be assigned different VMIDs than compute for the same PASID. Signed-off-by:
Graham Sider <Graham.Sider@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Ruijing Dong authored
Fixed some errors and warnings found by checkpatch.pl. Acked-by:
Ruijing Dong <ruijing.dong@amd.com> Signed-off-by:
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