- 03 Dec, 2010 24 commits
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Francisco Jerez authored
It needs a "strong" channel reference because it actually writes to the channel pushbuf, otherwise the corresponding FIFO context could get kicked off in the middle of nouveau_fence_sync(). Signed-off-by:
Francisco Jerez <currojerez@riseup.net> Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Francisco Jerez authored
Fences didn't increment the channel reference count, and the fenced channel could go away at any time. Fixes a potential race in nouveau_fence_update(). Signed-off-by:
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Francisco Jerez authored
nouveau_channel_ref() takes a "weak" channel reference that doesn't prevent the hardware channel resources from being released, it just keeps the channel data structure alive. Signed-off-by:
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Francisco Jerez authored
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Francisco Jerez authored
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Francisco Jerez authored
nouveau_channel_put() can be executed after the 'refcount == 0' check in nouveau_channel_get() and before the channel reference count is incremented. In that case CPU0 will take the context down while CPU1 thinks it owns the channel and 'refcount == 1'. Signed-off-by:
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Francisco Jerez authored
The destroy_context() engine hooks call gpuobj management functions to release the channel resources, these functions use HARDIRQ-unsafe locks whereas destroy_context() is called with the HARDIRQ-safe context_switch_lock held, that's a lock ordering violation. Push the engine-specific channel destruction logic into destroy_context() and let the hardware-specific code lock and unlock when it's actually needed. Change the engine destruction order to avoid a race in the small gap between pgraph and pfifo context uninitialization. Reported-by:
Marcin Slusarz <marcin.slusarz@gmail.com> Signed-off-by:
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Francisco Jerez authored
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Francisco Jerez authored
The pushbuf ioctl syncs after validation, no need for this anymore. Signed-off-by:
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
Not used at all yet, but lets hook it up now anyway. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
No other driver uses this, and userspace should be responsible for handling locking between them if they share BOs. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
This fixes a race condition between fbcon acceleration and TTM buffer moves. To reproduce: - start X - switch to vt and "while (true); do dmesg; done" - switch to another vt and "sleep 2 && cat /path/to/debugfs/dri/0/evict_vram" - switch back to vt running dmesg We don't make use of this on any other channel yet, they're currently protected by drm_global_mutex. This will change in the near future. Signed-off-by: -
Ben Skeggs authored
A future commit will add locking to the DRM's channel, and there's numerous problems that come up if we allow printk from an interrupt context to be accelerated. It seems saner to just disallow it completely. As a nice side-effect, all the "to accel or not to accel" logic gets moved out of the chipset-specific code. Signed-off-by: -
Ben Skeggs authored
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Dave Airlie authored
* 'drm-radeon-fusion' of ../drm-radeon-next: drm/radeon/kms: add Ontario APU ucode loading support drm/radeon/kms: add Ontario Fusion APU pci ids drm/radeon/kms: enable MSIs on fusion APUs drm/radeon/kms: add power table parsing support for Ontario fusion APUs drm/radeon/kms: refactor atombios power state fetching drm/radeon/kms: add bo blit support for Ontario fusion APUs drm/radeon/kms: add thermal sensor support for fusion APUs drm/radeon/kms: fill in GPU init for AMD Ontario Fusion APUs drm/radeon/kms: add radeon_asic struct for AMD Ontario fusion APUs drm/radeon/kms: evergreen.c updates for fusion drm/radeon/kms: MC setup changes for fusion APUs drm/radeon/kms: move r7xx/evergreen to its own vram_gtt setup function drm/radeon/kms: add support for ss overrides on Fusion APUs drm/radeon/kms: Add support for external encoders on fusion APUs drm/radeon/kms: atom changes for DCE4.1 devices drm/radeon/kms: add new family id for AMD Ontario APUs drm/radeon/kms: upstream power table updates drm/radeon/kms: upstream atombios.h updates drm/radeon/kms: upstream ObjectID.h updates drm/radeon/kms: setup mc chremap properly on r7xx/evergreen
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Dave Airlie authored
* 'drm-radeon-next' of ../drm-radeon-next: drm/radeon/kms: improve pflip precision on r1xx-r4xx drm/kms/radeon: Use high precision timestamps for pageflip completion events. drm/kms/radeon: Reorder vblank and pageflip interrupt handling. drm/radeon/kms: add pageflip ioctl support (v3) drm/kms/radeon: Add support for precise vblank timestamping.
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Dave Airlie authored
* drm-ttm-next: drm/radeon: Use the ttm execbuf utilities drm/ttm: Fix up io_mem_reserve / io_mem_free calling drm/ttm/vmwgfx: Have TTM manage the validation sequence. drm/ttm: Improved fencing of buffer object lists drm/ttm/radeon/nouveau: Kill the bo lock in favour of a bo device fence_lock drm/ttm: Don't deadlock on recursive multi-bo reservations drm/ttm: Optimize ttm_eu_backoff_reservation drm/ttm: Use kref_sub instead of repeatedly calling kref_put kref: Add a kref_sub function drm/ttm: Add a bo list reserve fastpath (v2)
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- 26 Nov, 2010 1 commit
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Alex Deucher authored
The update pending bit has a separate enable bit. Cc: Mario Kleiner <mario.kleiner@tuebingen.mpg.de> Signed-off-by:
Alex Deucher <alexdeucher@gmail.com> Signed-off-by:
Dave Airlie <airlied@redhat.com>
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- 22 Nov, 2010 15 commits
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Alex Deucher authored
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Alex Deucher authored
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Alex Deucher authored
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Alex Deucher authored
The vbios power tables on my inagua board seem a bit funky... Signed-off-by:
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Alex Deucher authored
The function was getting too large. Rework it to share more state better handle new power table formats. Signed-off-by:
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Alex Deucher authored
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Alex Deucher authored
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Alex Deucher authored
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Alex Deucher authored
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Alex Deucher authored
fusion chips only have 2 crtcs. Signed-off-by:
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Alex Deucher authored
- CONFIG_MEMSIZE is in bytes on fusion. - FB_BASE and FB_TOP are finer grained. Signed-off-by:
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Alex Deucher authored
MC_VM_FB_LOCATION is at a different offset between r6xx and r7xx/evergreen. The location is needed for vram setup on fusion chips. Signed-off-by:
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Alex Deucher authored
System specific spread spectrum overrides can be specified in the integrated system info table for Fusion APUs. This adds support for using those overrides. Signed-off-by:
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Alex Deucher authored
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Alex Deucher authored
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