- 14 Sep, 2010 6 commits
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Chris Wilson authored
As we currently may need to acquire a fence register during a modeset, we need to be able to do so in an uninterruptible manner. So expose that parameter to the callers of the fence management code. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
This ensures that we do wait upon the flushes to complete if necessary and avoid the visual tears, whilst enabling pipelined page-flips. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
It's a fixed size array so let the compiler do the hard work of updating all the call sites. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
I pulled the wrong version of the patch from Daniel Vetter which was missing the read barriers -- and the one that was causing all the trouble was from i915_gem_object_put_fence_reg(), leading to GPU hangs on gen3. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
By reducing the hangcheck frequency we check less often, conserving resources, and still detect a lock up quickly. On a fast machine with a slow GPU (like a Core2 paired with a 945G) it is easy for the hangcheck to misfire as we check too fast. Also once hung and if we fail to completely reset the chip, we have a nasty habit of proclaming a hang many times a second and generating a strobe-like display. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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- 13 Sep, 2010 7 commits
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Chris Wilson authored
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
Fix a regression in the previous regression fix... In order to turn off the pipes entirely upon the first modeset, we pretend that BIOS (or earlier module incarnation) left them active. The first task performed by setup_initial_configuration() is to disable all pipes and so to avoid skipping that step and so to ensure a known configuration we need to mark all the crtcs as active. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
When separating out the prepare/commit into its own separate functions we overlooked that the intel_crtc->dpms_mode was being used elsewhere to check on the actual status of the pipe. Track that bit of logic separately from the actual dpms mode, so there is no confusion should we be able to handle multiple dpms modes, nor any semantic conflict between prepare/commit and dpms. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
This closes a couple of corner cases where we introduced and forgot about a couple of routines that need to be called when disabling the crtc and then re-enabling it. The code needs to be moved again so that the common bits are shared across generations. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
One doesn't need to hold the mode lock in order to duplicate a mode. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
Commit 77d07fd9 introduced a regression where by not waiting for the panel to be turned off, left the panel and PLL registers locked across the modeset. Thus the panel remaining blank. As pointed out by Daniel Vetter, when testing LVDS it helps to open the laptop and look at the actual panel you are purporting to test. A second issue with the patch was that in order to modify the panel fitter before gen5, the pipe and the panel must have be completely powered down. So we wait. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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- 12 Sep, 2010 5 commits
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Chris Wilson authored
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
The documentation says that an SDVO command takes a maximum of 15us to be processed by the device, and that it is sufficient to read the status byte 3 times (whilst the command is still in the PENDING state) for the driver to be confident that sufficient time has elapsed. We err on the safe side and try 5 times before giving up. The only question that remains: was the old behaviour derived by experiments with real hardware? A look into the murky history of UMS, implies that the behaviour was accidental and the current retry mechanism was solely designed to catch the status byte indicating PENDING with no reference to hardware behaviour. (commit ac9181c014638dbeb334b40b4029d0ccb2b7a0fc in xf86-video-intel) Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
Avoid a potentially long busy-wait if we not in the process of atomically switching to the kdb console. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
We just assume that it will happen in a timely manner. A variant of this patch was first written and tested by Arjan van de Van. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
Just assume that it will turn off... Reported-by: Sitsofe Wheeler <sitsofe@yahoo.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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- 11 Sep, 2010 7 commits
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Chris Wilson authored
Remove our redundant udelay() as the timings are already handled by the i2c-algo-bit controller. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
The purpose is to make the code much easier to read and therefore reduce the possibility for bugs. A side effect is that it also makes it much easier for the compiler, reducing the object size by 4k -- from just a few functions! Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
Refactor the common code into seperate functions and use the MIN(large, small) buffer calculation for self-refresh watermarks. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
We need to track different state on each generation in order to detect when we need to refresh the FBC registers. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Jesse Barnes authored
Thermal reporting may not be enabled by default on some machines, so enable the appropriate bits to allow IPS to get the data it needs from the CPU thermal device. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
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- 10 Sep, 2010 13 commits
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Chris Wilson authored
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Jesse Barnes authored
This allows FDI error checking to work. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Jesse Barnes authored
TU size is only part of the M1 and M2 regs, not the N regs. This keeps us from overwriting a reserved field. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Jesse Barnes authored
Easier to read, and will pair up with a disable function. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Jesse Barnes authored
eDP panels require these to be set up prior to panel power sequencing, or they'll fail to power on due to an "asset not ready" check. And of course, eDP panels attached to anything other than DP_A need them enabled regardless, since they'll be driven from the CPU through FDI out to the PCH. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Jesse Barnes authored
This will allow us to optimize our prepare/commit paths a bit better. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> [ickle: minor tweak to handle the cursor across pipe resizing] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Jesse Barnes authored
This was just a workaround for some broken Ironlake CRTC code. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Jesse Barnes authored
So we can use it for CRTC prepare/commit. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Jesse Barnes authored
This way we can also use it in CRTC prepare/commit. Also makes it easier to split out FDI and other code. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
create_singlethreaded_workqueue() is being phased out for a new concurrency managed task infrastructure. Adapt our workqueue constructor to explicitly create a domain that only allows the execution of a single task at any time. All the tasks are expected to require the dev->struct_mutex, so would block concurrency of other tasks if we allow more than a single i915 task to be run at once. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Jesse Barnes authored
We don't know how to enable it safely, especially as outputs turn on and off. When disabling LP1 we also need to make sure LP2 and 3 are already disabled. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=29173 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=29082Reported-by: Chris Lord <chris@linux.intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Tested-by: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: stable@kernel.org Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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- 09 Sep, 2010 2 commits
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Chris Wilson authored
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
Currently we have a exact mapping of a connector onto an encoder for its whole lifetime. Make this an explicit property of the structure and so simplify the code. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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