- 26 Apr, 2024 40 commits
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Jesse Zhang authored
Check if ring is not a mes queue before freeing the wb entry, because we only allocate a wb entry when it's not a mes queue. Signed-off-by:
Jesse Zhang <jesse.zhang@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Bob Zhou authored
After amdgpu_i2c_get_byte fail, amdgpu_i2c_put_byte shouldn't be conducted to put wrong value. So return and check the i2c transfer result. Signed-off-by:
Bob Zhou <bob.zhou@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Bob Zhou authored
if the sdma_v4_0_irq_id_to_seq return -EINVAL, the process should be stop to avoid out-of-bounds read, so directly return -EINVAL. Signed-off-by:
Le Ma <le.ma@amd.com> Signed-off-by:
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Ma Jun authored
Initialize the interrupt timestamp for some legacy SOCs to fix the coverity issue "Uninitialized scalar variable" Signed-off-by:
Ma Jun <Jun.Ma2@amd.com> Suggested-by:
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YiPeng Chai authored
Use new interface to reserve bad page. Signed-off-by:
YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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YiPeng Chai authored
retired_page is page frame and should be expanded to the full address when querying status. Signed-off-by:
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Harish Kasiviswanathan authored
Queue buffer, though it is in system memory, has to be created using the correct amdgpu device. Enforce this as the BO needs to mapped to the GART for MES Hardware scheduler to access it. Signed-off-by:
Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Reviewed-by:
Felix Kuehling <felix.kuehling@amd.com> Reviewed-by:
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Dmytro Laktyushkin authored
Headless dp 2.0 will take longer to update. Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Rodrigo Siqueira authored
This commit add some missing HDMI control registers to DCN3x. Signed-off-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by:
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YiPeng Chai authored
support ACA logging ecc errors. Signed-off-by:
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YiPeng Chai authored
Add poison consumption handler. Signed-off-by:
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YiPeng Chai authored
Prepare to handle pasid poison consumption. Signed-off-by:
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YiPeng Chai authored
Retire bad pages for umc v12_0. Signed-off-by:
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YiPeng Chai authored
Add condition check for amdgpu_umc_fill_error_record. Signed-off-by:
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YiPeng Chai authored
Add delay work to retire bad pages. Signed-off-by:
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YiPeng Chai authored
1. umc v12_0 logs ecc errors. 2. Reserve newly detected ecc error pages. 3. Add tag for bad pages, so that they can be retired later. Signed-off-by:
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YiPeng Chai authored
Umc v12_0 converts error address. Signed-off-by:
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YiPeng Chai authored
Add interface to update umc v12_0 ecc status. Signed-off-by:
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YiPeng Chai authored
Add poison creation handler. Signed-off-by:
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YiPeng Chai authored
Prepare for logging ecc errors. Signed-off-by:
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YiPeng Chai authored
Add message fifo to handle RAS poison events. Signed-off-by:
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Jesse Zhang authored
Initialize the size before calling amdgpu_vce_cs_reloc, such as case 0x03000001. V2: To really improve the handling we would actually need to have a separate value of 0xffffffff.(Christian) Signed-off-by:
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Rodrigo Siqueira authored
Add TMDS balancer control to the list of available encoder registers for DCN 30. Signed-off-by:
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Srinivasan Shanmugam authored
This commit removes an unnecessary NULL check in the `dcn20_set_input_transfer_func` function in the `dcn20_hwseq.c` file. The variable `tf` is assigned the address of `plane_state->in_transfer_func` unconditionally, so it can never be `NULL`. Therefore, the check `if (tf == NULL)` is unnecessary and has been removed. The plane_state->in_transfer_func itself cannot be NULL because it's a structure, not a pointer. When we do tf = &plane_state->in_transfer_func;, we're getting the address of that structure, which will always be valid as long as plane_state itself is not NULL. we've already checked if plane_state is NULL with the line if (dpp_base == NULL || plane_state == NULL) return false;. So, if the code execution gets to the point where tf = &plane_state->in_transfer_func; is called, plane_state is guaranteed to be not NULL, and therefore tf will also not be NULL. drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn20/dcn20_hwseq.c 1094 bool dcn20_set_input_transfer_func(struct dc *dc, 1095 struct pipe_ctx *pipe_ctx, 1096 const struct dc_plane_state *plane_state) 1097 { 1098 struct dce_hwseq *hws = dc->hwseq; 1099 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 1100 const struct dc_transfer_func *tf = NULL; ^^^^^^^^^ This assignment is not necessary now. 1101 bool result = true; 1102 bool use_degamma_ram = false; 1103 1104 if (dpp_base == NULL || plane_state == NULL) 1105 return false; 1106 1107 hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state); 1108 hws->funcs.set_blend_lut(pipe_ctx, plane_state); 1109 1110 tf = &plane_state->in_transfer_func; ^^^^^ Before there was an if statement but now tf is assigned unconditionally 1111 --> 1112 if (tf == NULL) { ^^^^^^^^^^^^^^^^^ so these conditions are impossible. 1113 dpp_base->funcs->dpp_set_degamma(dpp_base, 1114 IPP_DEGAMMA_MODE_BYPASS); 1115 return true; 1116 } 1117 1118 if (tf->type == TF_TYPE_HWPWL || tf->type == TF_TYPE_DISTRIBUTED_POINTS) 1119 use_degamma_ram = true; 1120 1121 if (use_degamma_ram == true) { 1122 if (tf->type == TF_TYPE_HWPWL) 1123 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, Fixes the below Smatch static checker warning: drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn20/dcn20_hwseq.c:1112 dcn20_set_input_transfer_func() warn: address of 'plane_state->in_transfer_func' is non-NULL Fixes: 285a7054 ("drm/amd/display: Remove plane and stream pointers from dc scratch") Cc: Wenjing Liu <wenjing.liu@amd.com> Cc: Tom Chung <chiahsuan.chung@amd.com> Cc: Alvin Lee <alvin.lee2@amd.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Roman Li <roman.li@amd.com> Cc: Qingqing Zhuo <Qingqing.Zhuo@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Suggested-by:Dan Carpenter <dan.carpenter@linaro.org> Signed-off-by:
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Alex Deucher authored
We can't use a shared fence location because each transaction should be considered independently. Reviewed-by:
Shaoyun.liu <shaoyunl@amd.com> Signed-off-by:
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Rodrigo Siqueira authored
DCN3.0 supports some specific DWB debug registers that are not exposed yet. This commit just adds the missing registers. Signed-off-by:
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Melissa Wen authored
According to [1]: ``` DTN only logs 'pipe_count' instances of MPCC. However in some cases there are different number of MPCC than DPP (pipe_count). ``` As DTN log still relies on pipe_count to print mpcc state, switch to mpcc_count in all occurrences. [1] https://lore.kernel.org/amd-gfx/20240328195047.2843715-39-Roman.Li@amd.com/Reviewed-by:
Melissa Wen <mwen@igalia.com> Signed-off-by:
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Alex Deucher authored
As we use wb slots more dynamically, we need to lock access to avoid racing on allocation or free. Reviewed-by:
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Sonny Jiang authored
kmd_fw_shared changed in VCN5 Signed-off-by:
Sonny Jiang <sonny.jiang@amd.com> Reviewed-by:
Ruijing Dong <ruijing.dong@amd.com> Signed-off-by:
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David Tadokoro authored
In the header file dc/dcn301/dcn301_dccg.h, the function dccg301_create is declared twice, so remove duplication. Reviewed-by:
David Tadokoro <davidbtadokoro@usp.br> Signed-off-by:
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Mukul Joshi authored
Subtract the VRAM pinned memory when checking for available memory in amdgpu_amdkfd_reserve_mem_limit function since that memory is not available for use. Signed-off-by:
Mukul Joshi <mukul.joshi@amd.com> Reviewed-by:
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Sathishkumar S authored
jpeg ip version v2.1 and higher supports 16kx16k resolution decode Signed-off-by:
Sathishkumar S <sathishkumar.sundararaju@amd.com> Acked-by:
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Jose Fernandez authored
When slice_height is 0, the division by slice_height in the calculation of the number of slices will cause a division by zero driver crash. This leaves the kernel in a state that requires a reboot. This patch adds a check to avoid the division by zero. The stack trace below is for the 6.8.4 Kernel. I reproduced the issue on a Z16 Gen 2 Lenovo Thinkpad with a Apple Studio Display monitor connected via Thunderbolt. The amdgpu driver crashed with this exception when I rebooted the system with the monitor connected. kernel: ? die (arch/x86/kernel/dumpstack.c:421 arch/x86/kernel/dumpstack.c:434 arch/x86/kernel/dumpstack.c:447) kernel: ? do_trap (arch/x86/kernel/traps.c:113 arch/x86/kernel/traps.c:154) kernel: ? setup_dsc_config (drivers/gpu/drm/amd/amdgpu/../display/dc/dsc/dc_dsc.c:1053) amdgpu kernel: ? do_error_trap (./arch/x86/include/asm/traps.h:58 arch/x86/kernel/traps.c:175) kernel: ? setup_dsc_config (drivers/gpu/drm/amd/amdgpu/../display/dc/dsc/dc_dsc.c:1053) amdgpu kernel: ? exc_divide_error (arch/x86/kernel/traps.c:194 (discriminator 2)) kernel: ? setup_dsc_config (drivers/gpu/drm/amd/amdgpu/../display/dc/dsc/dc_dsc.c:1053) amdgpu kernel: ? asm_exc_divide_error (./arch/x86/include/asm/idtentry.h:548) kernel: ? setup_dsc_config (drivers/gpu/drm/amd/amdgpu/../display/dc/dsc/dc_dsc.c:1053) amdgpu kernel: dc_dsc_compute_config (drivers/gpu/drm/amd/amdgpu/../display/dc/dsc/dc_dsc.c:1109) amdgpu After applying this patch, the driver no longer crashes when the monitor is connected and the system is rebooted. I believe this is the same issue reported for 3113. Reviewed-by:
Jose Fernandez <josef@netflix.com> Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3113Signed-off-by:
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Rodrigo Siqueira authored
This commit add some missing debug registers for DPCS and RDPC debug. Signed-off-by:
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Sunil Khatri authored
Add ip dump for each ip of the asic in the devcoredump for all the ips where a callback is registered for register dump. Signed-off-by:
Sunil Khatri <sunil.khatri@amd.com> Reviewed-by:
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Sunil Khatri authored
Invoke the dump_ip_state function for each ip before the asic resets and save the register values for debugging via devcoredump. Signed-off-by:
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Sunil Khatri authored
Add support to print ip information to be used to print registers in devcoredump buffer. Signed-off-by:
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Sunil Khatri authored
Add the protoype for print ip state to be used to print the registers in devcoredump during a gpu reset. Signed-off-by:
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Sunil Khatri authored
Adding gfx10 gc registers to be used for register dump via devcoredump during a gpu reset. Signed-off-by:
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Sunil Khatri authored
Add the prototype to dump ip registers for all ips of different asics and set them to NULL for now. Based on the requirement add a function pointer for each of them. Signed-off-by:
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