- 13 Apr, 2015 14 commits
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Chris Wilson authored
This provides a nice boost to mesa in swap bound scenarios (as mesa throttles itself to the previous frame and given the scenario that will complete shortly). It will also provide a good boost to systems running with semaphores disabled and so frequently waiting on the GPU as it switches rings. In the most favourable of microbenchmarks, this can increase performance by around 15% - though in practice improvements will be marginal and rarely noticeable. v2: Account for user timeouts v3: Limit the spinning to a single jiffie (~1us) at most. On an otherwise idle system, there is no scheduler contention and so without a limit we would spin until the GPU is ready. v4: Drop forcewake - the lazy coherent access doesn't require it, and we have no reason to believe that the forcewake itself improves seqno coherency - it only adds delay. Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Eero Tamminen <eero.t.tamminen@intel.com> Cc: "Rantala, Valtteri" <valtteri.rantala@intel.com> Reviewed-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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Chandra Konduru authored
Enabling skylake panel fitting feature using shared scalers v2: -added force detach parameter for pfit disable purpose (me) -read crtc scaler state from hw state (Daniel) -replaced both skylake_pfit_enable and disable with skylake_pfit_update (me) -added scaler id check to intel_pipe_config_compare (Daniel) v3: -updated function header to kerneldoc format (Matt) -dropped need_scaling checks (Matt) v4: -move clearing of scaler id from commit path to check path (Matt) -updated colorkey checks based on recent updates (me) -squashed scaler check while enabling colorkey to here (me) -use values in plane_state->src as regular integers (me) -changes made not to modify state in commit path (Matt) v5: -squashed helper function to update scaler users to here (Matt) -squashed helper function to detach scaler to here (Matt, me) -changes to align with updated scaler structures (Matt, me) Signed-off-by:
Chandra Konduru <chandra.konduru@intel.com> Reviewed-by:
Matt Roper <matthew.d.roper@intel.com> Signed-off-by:
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Chandra Konduru authored
This is required for commit to perform as per staged assignment of scalers until atomic crtc commit function is available. As a place holder doing this copy from intel_atomic_commit for scaling to operate correctly. Signed-off-by:
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Chandra Konduru authored
From intel_atomic_check, call intel_atomic_setup_scalers() to assign scalers based on staged scaling requests. Fail the transaction if setup returns error. Setting up of scalers should be moved to atomic crtc check once atomic crtc is ready. v2: -updated parameter passing to setup_scalers (me) Signed-off-by:
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Chandra Konduru authored
Added intel_atomic_setup_scalers to setup scalers based on staged scaling requests from a crtc and its planes. If staged requests are supportable, this function assigns scalers to requested planes and crtc. Note that the scaler assignement itself is staged into crtc_state and respective plane_states for later commit after all checks have been done. overall high level flow: - scaler requests are staged into crtc_state by planes/crtc - check whether staged scaling requests can be supported - add planes using scalers that aren't in current transaction - assign scalers to requested users - as part of plane commit, scalers will be committed (i.e., either attached or detached) to respective planes in hw - as part of crtc_commit, scaler will be either attached or detached to crtc in hw crtc_compute_config calls intel_atomic_setup_scalers() to start scaler assignments as per scaler state in crtc config. This call should be moved to atomic crtc once it is available. v2: -removed a log message (me) -changed input parameter to crtc_state (me) v3: -remove assigning plane_state returned by drm_atomic_get_plane_state (Matt) -fail if there is an error from drm_atomic_get_plane_state (Matt) v4: -changes to align with updated scaler structure (Matt, me) v5: -added addtional checks before enabling HQ mode (me) -added comments to enable HQ mode (Matt) Signed-off-by:
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Chandra Konduru authored
crtc_state is cleared during mode set which wipes out complete scaler state too. This is causing issues. To fix, ensure scaler state is preserved because it contains not only crtc scaler usage, but also planes using scalers on this crtc. Signed-off-by:
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Chandra Konduru authored
Dumps scaler state as part of dumping crtc_state. v2: -use regular ints from plane_state->src (me) v3: -changes to align with updated scaler structures (Matt) -interpret plane_state->src as 16.16 format (Matt, Daniel) Signed-off-by:
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Chandra Konduru authored
This patch keeps intel_plane_state->src rect back into 16.16 format. v2: -sprite src rect to match primary format (Matt, Daniel) v3: -moved a hunk from #14 to keep src rect in check & commit in tandom (Matt) Signed-off-by:
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Chandra Konduru authored
Initializing scalers with supported values during crtc init. v2: -initialize single copy of min/max values (Matt) v3: -moved gen check to callsite (Matt) v4: -squashed planes begin with no scaler to here (me) v5: -updated init function with updated scaler state structure (Matt) Signed-off-by:
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Chandra Konduru authored
This patch initializes plane colorkey to NONE. Signed-off-by:
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Chandra Konduru authored
skylake scaler structure definitions. scalers live in crtc_state as they are pipe resources. They can be used either as plane scaler or panel fitter. scaler assigned to either plane (for plane scaling) or crtc (for panel fitting) is saved in scaler_id in plane_state or crtc_state respectively. scaler_id is used instead of scaler pointer in plane or crtc state to avoid updating scaler pointer everytime a new crtc_state is created. v2: -made single copy of min/max values for scalers (Matt) v3: -updated commentary for scaler_id (me) v4: -converted src/dst ranges to #defines, dropped ratios (Matt) Signed-off-by:
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Chandra Konduru authored
Adding register definitions for skylake scalers. v2: -add #define for plane selection mask (me) Signed-off-by:
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Sagar Kamble authored
When RC6 along with Render power gating is enabled, GPU hang happens due to lack of synchronization between GTI and Render power gating. v2: Updated commit message and WA name (Damien) Change-Id: If1614206341eb52a21eadae8c5ebb2655029b50c Reviewed-by:
Damien Lespiau <damien.lespiau@intel.com> Signed-off-by:
Sagar Kamble <sagar.a.kamble@intel.com> Signed-off-by:
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Ander Conselvan de Oliveira authored
Connector states were being allocated in intel_setup_outputs() in loop over all connectors. That meant hot-added connectors would have a NULL state. Since the change to use a struct drm_atomic_state for the legacy modeset, connector states are necessary for the i915 driver to function properly, so that would lead to oopses. v2: Fix test for intel_connector_init() success in lvds and sdvo (PRTS) Signed-off-by:
Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reported-and-tested-by:
Nicolas Kalkhof <nkalkhof@web.de> Signed-off-by:
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- 10 Apr, 2015 26 commits
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Michel Thierry authored
After commit d7b9ca2f ("drm/i915: Remove request->uniq") dev_priv is no longer needed. Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
Michel Thierry <michel.thierry@intel.com> Signed-off-by:
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Jani Nikula authored
Fix DEBUG_FS=n build broken by commit aa7471d2 Author: Jani Nikula <jani.nikula@intel.com> Date: Wed Apr 1 11:15:21 2015 +0300 drm/i915: add i915 specific connector debugfs file for DPCD Reported-by:
kbuild test robot <fengguang.wu@intel.com> Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Signed-off-by:
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Mika Kuoppala authored
Move to i915_vma_bind as it is part of the binding. Suggested-by:
Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by:
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Sonika Jindal authored
v2: Moving creation of property in a function, checking for 90/270 rotation simultaneously (Chris) Letting primary plane to be positioned v3: Adding if/else for 90/270 and rest params programming, adding check for pixel_format, some cleanup (review comments) v4: Adding right pixel_formats, using src_* params instead of crtc_* for offset and size programming (Ville) v5: Rebased on -nightly and Tvrtko's series for gtt remapping. v6: Rebased on -nightly (Tvrtko's series merged) v7: Moving pixel_format check to intel_atomic_plane_check (Matt) Signed-off-by:
Sonika Jindal <sonika.jindal@intel.com> Reviewed-by:
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Sonika Jindal authored
Signed-off-by:
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Sagar Kamble authored
Change-Id: I4253459c075c50d9b6f034b4ed4ad2f54cd7d1d7 Signed-off-by:
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Ander Conselvan de Oliveira authored
Since the following commit, the PLL calculations are done earlier, so the code following the comment doesn't do anything PLL or encoder related. It only updates the primary plane now. commit f3019a4d Author: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Date: Wed Oct 29 11:32:37 2014 +0200 drm/i915: Remove crtc_mode_set() hook Signed-off-by:
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Chris Wilson authored
When looking for viable candidates to shrink, we only want objects that are not pinned. However to do so we performed a double iteration over the vma in the objects, first looking for the pin-count, then looking for allocations. We can do both at once and be slightly more explicit in our validity test. Signed-off-by:
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Chris Wilson authored
As we never expose context objects directly to userspace, we can forgo allocating a first-class GEM object for them and prefer to use the limited resource of reserved/stolen memory for them. Note this means that their initial contents are undefined. However, a downside of using stolen objects for execlists is that we cannot access the physical address directly (thanks MCH!) which prevents their use. Signed-off-by:
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Chris Wilson authored
We already assign a unique identifier to every request: seqno. That someone felt like adding a second one without even mentioning why and tweaking ABI smells very fishy. Fixes regression from commit b3a38998 Author: Nick Hoath <nicholas.hoath@intel.com> Date: Thu Feb 19 16:30:47 2015 +0000 drm/i915: Fix a use after free, and unbalanced refcounting v2: Rebase Signed-off-by:
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Chris Wilson authored
Signed-off-by:
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Chris Wilson authored
Remove some needless variables and parameter passing. Signed-off-by:
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Chris Wilson authored
Similar in vain in reducing the number of unrequired spinlocks used for execlist command submission (where the forcewake is required but manually controlled), we know that the IRQ registers are outside of the powerwell and so we can access them directly. Since we now have direct access exported via I915_READ_FW/I915_WRITE_FW, lets put those to use in the irq handlers as well. In the process, reorder the execlist submission to happen as early as possible. v2: Restrict the untraced register mmio to just the GT path (i.e. the hotpath for execlists) Signed-off-by:
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Chris Wilson authored
This eliminates six needless spin lock/unlock pairs when writing out ELSP. v2: Respin with my preferred colour. v3: Mostly back to the original colour Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> [v1] Signed-off-by:
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Daniel Vetter authored
Already tagged this one and 0-day builder is failing me. Signed-off-by:Daniel Vetter <daniel.vetter@intel.com>
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Chris Wilson authored
vma are more frequently allocated than objects and so should equally benefit from having a dedicated slab. Signed-off-by:
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Chris Wilson authored
requests are even more frequently allocated than objects and equally benefit from having a dedicated slab. v2: Rebase Signed-off-by:
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Matt Roper authored
Once we have full atomic modeset, these kind of flags should be in a real intel_crtc_state that's tracked properly. In the meantime, make sure we clear out any old flags at the beginning of a transaction so that we don't wind up seeing leftover flags from old transactions that were checked, but never went to the commit step. At the moment, a failed check or prepare could leave stale flags behind that interfere with the next atomic transaction. v2: Just do a memset; the series this patch was originally part of placed additional fields into the structure that shouldn't be cleared, but that's no longer the case. Signed-off-by: -
Matt Roper authored
Switch from our plane update/disable entrypoints to use the full atomic helpers (which generate a top-level atomic transaction) rather than the transitional helpers (which only create/manipulate orphaned plane states independent of a top-level transaction). Various upcoming work (SKL scalers, atomic watermarks, etc.) requires a full atomic transaction to behave properly/cleanly. Last time we tried this, we had to back out the change because we still call the drm_plane vfuncs directly from within our legacy modesetting code. This potentially results in nested atomic transactions, locking collisions, and other failures. To avoid that problem again, we sidestep the issue by calling the transitional helpers directly (rather than through a vfunc) when we're nested inside of other legacy modesetting code. However this does allow legacy SetPlane() ioctl's to process an entire drm_atomic_state transaction, which is important for upcoming patches. Cc: Chandra Konduru <chandra.konduru@intel.com> Signed-off-by:
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Daniel Vetter authored
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Chandra Konduru authored
Adding drm helper function to return plane pointer from index where index is a returned by drm_plane_index. v2: -avoided nested loop by adding loop count (Daniel) v3: -updated patch header prefix to 'drm' (Matt) v4: -fixed a kerneldoc issue (kbuild-internal) Cc: dri-devel@lists.freedesktop.org Signed-off-by:
Dave Airlie <airlied@redhat.com> Signed-off-by:
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Chris Wilson authored
After the removal of DRI1, all access to the rings are through requests and so we can always be sure that there is a request to wait upon to free up available space. The fallback code only existed so that we could quiesce the GPU following unmediated access by DRI1. v2: Rebase Signed-off-by:
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Chris Wilson authored
When we submit a request to the GPU, we first take the rpm wakelock, and only release it once the GPU has been idle for a small period of time after all requests have been complete. This means that we are sure no new interrupt can arrive whilst we do not hold the rpm wakelock and so can drop the individual get/put around every single request inside execlists. Note: to close one potential issue we should mark the GPU as busy earlier in __i915_add_request. To elaborate: The issue is that we emit the irq signalling sequence before we grab the rpm reference, which means we could miss the resulting interrupt (since that's not set up when suspended). The only bad side effect is a missed interrupt, gt mmio writes automatically wake up the hw itself. But otoh we have an umbrella rpm reference for the entirety of execbuf, as long as that's there we're covered. Signed-off-by:
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Chris Wilson authored
We can use the simpler spinlock form to disable interrupts as we are always outside of an irq/softirq handler. Signed-off-by:
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Ville Syrjälä authored
Recent BSW VBT has a VBT child device size 37 bytes instead of the 33 bytes our code assumes. This means we fail to parse the VBT and thus fail to detect eDP ports properly and just register them as DP ports instead. Fix it up by using the reported child device size from the VBT instead of assuming it matches out struct defintions. The latest spec I have shows that the child device size should be 36 bytes for rev >= 195, however on my BSW the size is actually 37 bytes. And our current struct definition is 33 bytes. Feels like the entire VBT parses would need to be rewritten to handle changes in the layout better, but for now I've decided to do just the bare minimum to get my eDP port back. Cc: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com> Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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Michel Thierry authored
True PPGTT is capable of having a full address space, even if the system has less allocated memory. Note that aliasing PPGTT always aliases the GGTT and thus should remain of the same size. Signed-off-by:
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