- 16 Sep, 2020 5 commits
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Rikard Falkeborn authored
cdns_nxp_sequence_pair[] are never modified and can be made const to allow the compiler to put them in read-only memory. Signed-off-by:
Rikard Falkeborn <rikard.falkeborn@gmail.com> Reviewed-by:
Peter Chen <peter.chen@nxp.com> Link: https://lore.kernel.org/r/20200912204639.501669-3-rikard.falkeborn@gmail.comSigned-off-by:
Vinod Koul <vkoul@kernel.org>
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Rikard Falkeborn authored
The static cdns_reg_pairs and regmap_config structs are not modified and can be made const. This allows the compiler to put them in read-only memory. Signed-off-by:
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Vinod Koul authored
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Swapnil Jakhade authored
Set Torrent PHY attributes bus_width, max_link_rate and mode for DisplayPort. Signed-off-by:
Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by:
Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/1599805114-22063-3-git-send-email-sjakhade@cadence.comSigned-off-by:
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Swapnil Jakhade authored
Add new PHY attribute max_link_rate to struct phy_attrs. This indicates maximum link rate supported by PHY (in Mbps). Signed-off-by:
Yuti Amonkar <yamonkar@cadence.com> Signed-off-by:
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- 11 Sep, 2020 2 commits
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Ramuthevar Vadivel Murugan authored
Add support for USB PHY on Intel LGM SoC. Signed-off-by:
Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> Reviewed-by:
Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20200828022312.52724-3-vadivel.muruganx.ramuthevar@linux.intel.comSigned-off-by:
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Ramuthevar Vadivel Murugan authored
Add the dt-schema to support USB PHY on Intel LGM SoC Signed-off-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20200828022312.52724-2-vadivel.muruganx.ramuthevar@linux.intel.comSigned-off-by:
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- 08 Sep, 2020 10 commits
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Roger Quadros authored
Move ti,omap-usb2 to its own YAML schema. Signed-off-by:
Roger Quadros <rogerq@ti.com> Reviewed-by:
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Grygorii Strashko authored
On K3 AM654x/J721E platforms the Port MII mode selection register(s) have similar format and placed in the System Control Module (SCM) module sequentially as one register per port, but, depending SOC and CPSW instance, the base offset and number of ports can be different. Hence, add possibility to retrieve number of ports and base registers offset from DT and support for max possible number of ports supported by K3 SoCs like J721E. Signed-off-by:
Grygorii Strashko <grygorii.strashko@ti.com> Link: https://lore.kernel.org/r/20200828201943.29155-4-grygorii.strashko@ti.comSigned-off-by:
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Grygorii Strashko authored
Use features mask during PHYs initialization to simplify code. Signed-off-by:
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Grygorii Strashko authored
Move phy initialization in separate function to improve code readability and simplify future changes. Signed-off-by:
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Chunfeng Yun authored
Use readl_poll_timeout() to simplify code Signed-off-by:
Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/1598320987-25518-6-git-send-email-chunfeng.yun@mediatek.comSigned-off-by:
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Chunfeng Yun authored
Use readl_poll_timeout() to simplify code Signed-off-by:
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Chunfeng Yun authored
Use readl_relaxed_poll_timeout() to simplify code, rename local function read_poll_timeout() as poll_timeout() to avoid repeated definition Signed-off-by:
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Chunfeng Yun authored
Use readl_poll_timeout_atomic() to simplify code Signed-off-by:
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Chunfeng Yun authored
Use readl_poll_timeout_atomic() to simplify code Signed-off-by:
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Chunfeng Yun authored
Use readl_poll_timeout_atomic() to simplify code Signed-off-by:
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- 31 Aug, 2020 16 commits
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Ezequiel Garcia authored
There is no need for this driver to be in staging. Let's promote it! Signed-off-by:
Ezequiel Garcia <ezequiel@collabora.com> Link: https://lore.kernel.org/r/20200825220710.634106-1-ezequiel@collabora.comSigned-off-by:
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Kunihiko Hayashi authored
Add a driver for PHY interface built into ahci controller implemented in UniPhier SoCs. This supports PXs2 and PXs3 SoCs. Signed-off-by:
Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/1598352071-26675-3-git-send-email-hayashi.kunihiko@socionext.comSigned-off-by:
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Kunihiko Hayashi authored
Add DT bindings for PHY interface built into ahci controller implemented in UniPhier SoCs. Signed-off-by:
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Rikard Falkeborn authored
Their only usages is to assign the address to the data field in the of_device_id struct, which is a const void pointer. Make them const to allow the compiler to put them in read-only memory. Signed-off-by:
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Rikard Falkeborn authored
The only usage is to pass its address to devm_phy_create() which takes a const pointer. Make it const to allow the compiler to put it in read-only memory. Signed-off-by:
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Rikard Falkeborn authored
The only usage is to pass its address to devm_phy_create() which takes a const pointer. Make it const to allow the compiler to put it in read-only memory. Signed-off-by:
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Rikard Falkeborn authored
The only usage is to pass its address to devm_phy_create() which takes a const pointer. Make it const to allow the compiler to put it in read-only memory. Signed-off-by:
Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20200823220025.17588-6-rikard.falkeborn@gmail.comSigned-off-by:
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Rikard Falkeborn authored
The only usage is to pass its address to devm_phy_create() which takes a const pointer. Make it const to allow the compiler to put it in read-only memory. Signed-off-by:
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Rikard Falkeborn authored
The only usage is to pass its address to devm_phy_create() which takes a const pointer. Make it const to allow the compiler to put it in read-only memory. Signed-off-by:
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Rikard Falkeborn authored
The only usage is to pass its address to devm_phy_create() which takes a const pointer. Make it const to allow the compiler to put it in read-only memory. Signed-off-by:
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Rikard Falkeborn authored
The only usage is to pass its address to devm_phy_create() which takes a const pointer. Make it const to allow the compiler to put it in read-only memory. Signed-off-by:
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Li Jun authored
Add initial support for imx8mp usb phy support, imx8mp usb has a silimar phy as imx8mq, which has some different customizations on clock and low power design when SoC integration. Signed-off-by:
Li Jun <jun.li@nxp.com> Link: https://lore.kernel.org/r/1598276014-2377-2-git-send-email-jun.li@nxp.comSigned-off-by:
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Li Jun authored
Add "fsl,imx8mp-usb-phy" compatible string for imx8mp usb phy, which is similar with imx8mq usb phy but with some different customizations. Acked-by:
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Roger Quadros authored
Fix checkpatch warnings and sort the include files alphabetically. Signed-off-by:
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Vinod Koul authored
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Roger Quadros authored
AM654x PG1.0 has a silicon bug that D+ is pulled high after POR, which could cause enumeration failure with some USB hubs. Disabling the USB2_PHY Charger Detect function will put D+ into the normal state. This addresses Silicon Errata: i2075 - "USB2PHY: USB2PHY Charger Detect is Enabled by Default Without VBUS Presence" Signed-off-by:
Jan Kiszka <jan.kiszka@siemens.com> Link: https://lore.kernel.org/r/20200824075127.14902-2-rogerq@ti.comSigned-off-by:
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- 23 Aug, 2020 6 commits
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YueHaibing authored
Remove duplicate include file Signed-off-by:
YueHaibing <yuehaibing@huawei.com> Link: https://lore.kernel.org/r/20200818114721.55464-1-yuehaibing@huawei.comSigned-off-by:
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Sivaprakash Murugesan authored
There were some problem in ipq8074 Gen2 PCIe phy init sequence. 1. Few register values were wrongly updated in the phy init sequence. 2. The register QSERDES_RX_SIGDET_CNTRL is a RX tuning parameter register which is added in serdes table causing the wrong register was getting updated. 3. Clocks and resets were not added in the phy init. Fix these to make Gen2 PCIe port on ipq8074 devices to work. Fixes: eef243d0 ("phy: qcom-qmp: Add support for IPQ8074") Cc: stable@vger.kernel.org Co-developed-by:
Selvam Sathappan Periakaruppan <speriaka@codeaurora.org> Signed-off-by:
Sivaprakash Murugesan <sivaprak@codeaurora.org> Link: https://lore.kernel.org/r/1596036607-11877-4-git-send-email-sivaprak@codeaurora.orgSigned-off-by:
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Sekhar Nori authored
Update PCIe serdes config to latest suggested for hardware. This fixes cases of failure to enumerate in Gen2 mode with some cards. Signed-off-by:
Sekhar Nori <nsekhar@ti.com> Link: https://lore.kernel.org/r/20200727194603.44636-4-nsekhar@ti.com [fix typo threshold] Signed-off-by:
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Sekhar Nori authored
Checking return value after each regfield write becomes hard to read quickly as number of writes increase. Simplify by checking for error only once. Signed-off-by:
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Sekhar Nori authored
regfield handling in current driver code is made complicated by having a separate regfield variable for each field which is allocated individually. This quickly gets unwieldy once number of regfields increase. Instead, use an array of regfields which are allocated in a loop. Signed-off-by:
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Anand Moon authored
Instead of a busy waiting while loop using udelay use readl_poll_timeout function to check the condition is met or timeout occurs in crport_handshake function. readl_poll_timeout is called in non atomic context so it safe to sleep until the condition is met. Signed-off-by:
Anand Moon <linux.amoon@gmail.com> Link: https://lore.kernel.org/r/20200720173502.542-1-linux.amoon@gmail.comSigned-off-by:
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- 17 Aug, 2020 1 commit
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Wei Yongjun authored
In case of error, the function devm_ioremap() returns NULL pointer not ERR_PTR(). The IS_ERR() test in the return value check should be replaced with NULL test. Fixes: ef19b117 ("phy: qualcomm: add qcom ipq806x dwc usb phy driver") Reported-by:
Hulk Robot <hulkci@huawei.com> Signed-off-by:
Wei Yongjun <weiyongjun1@huawei.com> Link: https://lore.kernel.org/r/20200723113622.136752-1-weiyongjun1@huawei.comSigned-off-by:
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