- 17 Jan, 2023 7 commits
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Konrad Dybcio authored
Rename the reserved-memory subnodes such that they don't use undescores. Signed-off-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230116141451.470158-1-konrad.dybcio@linaro.org
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Kuogee Hsieh authored
Move data-lanes property from mdss_dp node to dp_out endpoint. Also add link-frequencies property into dp_out endpoint as well. The last frequency specified at link-frequencies will be the max link rate supported by DP. Signed-off-by:
Kuogee Hsieh <quic_khsieh@quicinc.com> Signed-off-by:
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Krzysztof Kozlowski authored
Bindings expect DAI children to be named "dai-link": sc7180-trogdor-coachz-r1.dtb: lpass@62d87000: Unevaluated properties are not allowed ('hdmi@5', 'mi2s@0', 'mi2s@1' were unexpected) Signed-off-by:Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by:
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Krzysztof Kozlowski authored
Display clock controller bindings do not allow power-domain-names: sm8350-hdk.dtb: clock-controller@af00000: 'power-domain-names' does not match any of the regexes: 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml Signed-off-by:
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Dmitry Baryshkov authored
Remove manually created symbol clocks and replace them with clocks provided by PHY. Reviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by:
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Dmitry Baryshkov authored
Enable PCIe0 and PCIe1 hosts found on SM8350 HDK board. Signed-off-by:
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Dmitry Baryshkov authored
Add PCIe0 and PCIe1 (and corresponding PHY) devices found on SM8350 platform. The PCIe0 is a 1-lane Gen3 host, PCIe1 is a 2-lane Gen3 host. Signed-off-by:
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- 12 Jan, 2023 4 commits
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Bjorn Andersson authored
While MDSS_GDSC is a subdomain of MMCX, Linux does not respect this relationship and sometimes invokes sync_state on the rpmhpd (MMCX) before the DisplayPort controller has had a chance to probe. The result when this happens is that the power is lost to the multimedia subsystem between the probe of msm_drv and the DisplayPort controller - which results in an irrecoverable state. While this is an implementation problem, this aligns the power domain setting of the one DP instance with that of all the others. Fixes: 57d6ef68 ("arm64: dts: qcom: sc8280xp: Define some of the display blocks") Signed-off-by:
Bjorn Andersson <quic_bjorande@quicinc.com> Reviewed-by:
Johan Hovold <johan+linaro@kernel.org> Reviewed-by:
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Johan Hovold authored
The vreg_l3b supply is used by the eDP, UFS and USB1 PHYs which are now described by the devicetree so that the regulator no longer needs to be marked always-on. Signed-off-by:
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Mukesh Ojha authored
Add TCSR register space and refer it from scm node, so that it can be used by SCM driver. Signed-off-by:
Mukesh Ojha <quic_mojha@quicinc.com> Signed-off-by:
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Bjorn Andersson authored
Running GCC_USB30_*_MASTER_CLK at 200MHz requires CX at nominal level, not doing so results in occasional lockups. This was previously hidden by the fact that the display stack incorrectly voted for CX (instead of MMCX). Fixes: 152d1faf ("arm64: dts: qcom: add SC8280XP platform") Signed-off-by:
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- 11 Jan, 2023 29 commits
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Dmitry Baryshkov authored
Drop the virtual ipa-virt device. The interconnects it provided are going to be represented as <&rpmhcc RPMH_IPA_CLK> clock. Signed-off-by:
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Dmitry Baryshkov authored
Drop the virtual ipa-virt device. The interconnects it provided are going to be represented as <&rpmhcc RPMH_IPA_CLK> clock. Signed-off-by:
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Luca Weiss authored
Add a node describing the ADC5_BAT_ID_100K_PU channel with the properties taken from downstream kernel. Signed-off-by:
Luca Weiss <luca.weiss@fairphone.com> Reviewed-by:
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Stephan Gerhold authored
i2c-qup allows using DMA to speed up larger transfers. In msm8916.dtsi the DMA channels are already assigned to the SPI controllers but missing for I2C. Add them there as well. This also fixes confusing errors in dmesg for each I2C controller: i2c_qup 78b6000.i2c: tx channel not available Signed-off-by:
Stephan Gerhold <stephan@gerhold.net> Reviewed-by:
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Stephan Gerhold authored
Adding the "dmas" to the I2C controllers prevents probing them if blsp_dma is disabled (infinite probe deferral). Avoid this by enabling blsp_dma by default - it's an integral part of the SoC that is almost always used (even if just for UART). Signed-off-by:
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Lin, Meng-Bo authored
FL8005A uses Qualcomm GPIO flash LEDs which is compatible with SGM3140 Flash LED driver. Add it to the device tree. Signed-off-by:
Lin, Meng-Bo <linmengbo0689@protonmail.com> Reviewed-by:
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Lin, Meng-Bo authored
FL8005A uses a Focaltech FT5402 touchscreen that is connected to blsp_i2c5. Add it to the device tree. Signed-off-by:
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Lin, Meng-Bo authored
GPLUS FL8005A is a tablet using the MSM8916 SoC released in 2015. Add a device tree for with initial support for: - GPIO keys - GPIO LEDs - pm8916-vibrator - SDHCI (internal and external storage) - USB Device Mode - UART - WCNSS (WiFi/BT) - Regulators Signed-off-by:
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Dmitry Baryshkov authored
Now as we added the APCS clock controller support, mark apcs device as clock provider by adding #clock-cells property. Signed-off-by:
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Johan Hovold authored
The SA8540P PMICs are named PMM8540. Rename the devicetree source labels to reflect this. Reviewed-by:
Brian Masney <bmasney@redhat.com> Reviewed-by:
Eric Chanudet <echanude@redhat.com> Signed-off-by:
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Johan Hovold authored
Add the missing interrupt-controller include which is needed by the RTC node. Reviewed-by:
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Johan Hovold authored
Enable the eDP display on MDSS0 DP3, including backlight control. Signed-off-by:
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Bjorn Andersson authored
The SA8295P ADP has, among other interfaces, six MiniDP connectors which are connected to MDSS0 DP2 and DP3, and MDSS1 DP0 through DP3. Enable Display Clock controllers, MDSS instanced, MDPs, DP controllers, DP PHYs and link them all together. Signed-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by:
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Bjorn Andersson authored
The SC8280XP CRD has a EDP display on MDSS0 DP3, enable relevant nodes and link it together with the backlight control. Signed-off-by:
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Bjorn Andersson authored
Define the display clock controllers, the MDSS instances, the DP phys and connect these together. Signed-off-by:
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Bjorn Andersson authored
This reverts commit 92ad27fb, as this was applied to the wrong branch and causes merge conflicts.
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Dmitry Baryshkov authored
14nm DSI PHY has the only supply, vcca. Drop the extra vdda-supply. Fixes: 5a134c94 ("arm64: dts: qcom: msm8996: add support for oneplus3(t)") Signed-off-by:
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Marijn Suijten authored
Tama has four GPIO-wired keys: two for camera focus and shutter / snapshot, and two more for volume up and down. As per the comment these used to not work because the necessary pin bias was missing, which is now set via pinctrl on pm8998_gpios. The missing bias has also been added to the existing volume down button, which receives a node name and label cleanup at the same time to be more consistent with other DTS and the newly added buttons. Its deprecated gpio-key,wakeup property has also been replaced with wakeup-source. Note that volume up is also available through the usual PON RESIN node, but unlike other platforms only triggers when the power button is held down at the same time making it unsuitable to serve as KEY_VOLUMEUP. Fixes: 30a7f99b ("arm64: dts: qcom: Add support for SONY Xperia XZ2 / XZ2C / XZ3 (Tama platform)") Reviewed-by:
Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by:
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Dmitry Baryshkov authored
Drop the #clock-cells (probably a leftover from the times before the DP PHY split) Fixes: eaac4e55 ("arm64: dts: qcom: sdm845: add displayport node") Signed-off-by:
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Konrad Dybcio authored
Feed GCC and SDHC_2 with the RPM XO instead of the fixed-clock one. Signed-off-by:
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Manivannan Sadhasivam authored
Both PCIe0 and PCIe1 controllers are capable of signalling the MSIs received from endpoint devices to the CPU using GIC-ITS MSI controller. Add support for it. Currently, BDF (0:0.0) and BDF (1:0.0) are enabled and with the msi-map-mask of 0xff00, all the 32 devices under these two busses can share the same Device ID. The GIC-ITS MSI implementation provides an advantage over internal MSI implementation using Locality-specific Peripheral Interrupts (LPI) that would allow MSIs to be targeted for each CPU core. It should be noted that the MSIs for BDF (1:0.0) only works with Device ID of 0x5980 and 0x5a00. Hence, the IDs are swapped. Signed-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Tested-by: Konrad Dybcio <konrad.dybcio@linaro.org> # Xperia 1 IV (WCN6855) Signed-off-by:
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Krzysztof Kozlowski authored
Add missingh whitespace between node name/label and opening {. Signed-off-by: -
Dmitry Baryshkov authored
The test clock apparently it's not used by anyone upstream. Remove it. Reviewed-by:
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Krzysztof Kozlowski authored
The bindings expect second Soundwire interrupt to be "wakeup" (Linux driver takes by index): sm8450-hdk.dtb: soundwire-controller@33b0000: interrupt-names:1: 'wakeup' was expected Fixes: 14341e76 ("arm64: dts: qcom: sm8450: add Soundwire and LPASS") Signed-off-by:
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Eric Chanudet authored
A few descriptions including a qcom,pm8941-rtc describe two reg-names for the "rtc" and "alarm" register banks, but only one offset. For consistency with reg-names, add the "alarm" register offset. No functional change is expected from this. Signed-off-by:
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Eric Chanudet authored
Include the dtsi to use a single pmic descriptions. Both sa8295p-adp and sa8540p-adp have the same spmi pmic apparently. Signed-off-by:
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Eric Chanudet authored
Add the rtc block on the first pmic to enable the rtc for sa8540p-ride. Signed-off-by:
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Eric Chanudet authored
pm8450a.dtsi was introduced for the descriptions of pmics used on sa8540p based boards. Rename the dtsi to make this relationship explicit. Signed-off-by:
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Konrad Dybcio authored
SM8350 is one of the last SoCs whose DTSI escaped the smem node conversion. Use the newer memory-node binding instead of a memory *and* smem node. Signed-off-by:
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