- 07 Jul, 2022 7 commits
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Alex Deucher authored
It's not used outside of dcn30_resource.c. Reported-by:
kernel test robot <lkp@intel.com> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Fixes the following: drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_hwseq.c:428:33: warning: variable 'old_pipe' set but not used Reported-by:
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Eric Huang authored
It is to avoid unnecessary queue eviction when range is not mapped to gpu. Signed-off-by:
Eric Huang <jinhuieric.huang@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Evan Quan authored
[Why] The return value indicates whether the operation(disable/enable) succeeded or not. The existing logic reports wrong result even if the disablement was performed successfully. That will make succeeding reenablement abandoned as dc->idle_optimizations_allowed is always true. [How] Correct the return value to reflect the real result of disablement. Fixes: 235c6763 ("drm/amd/display: add DCN32/321 specific files for Display Core") Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
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Aurabindo Pillai authored
[Why&How] The debug option to disable idle power optimization can be dropped Fixes: 235c6763 ("drm/amd/display: add DCN32/321 specific files for Display Core") Signed-off-by:
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Eric Huang authored
Adding always evict queues when flag is set to KFD_IOCTL_SVM_FLAG_GPU_ALWAYS_MAPPED as if XNACK off. Signed-off-by:
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Eric Huang authored
It is to add new option for always keeping gpu mapping. Signed-off-by:
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- 05 Jul, 2022 33 commits
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Alex Deucher authored
Seems to break hibernation. Disable for now until we can root cause it. Fixes: 087451f3 ("drm/amdgpu: use generic fb helpers instead of setting up AMD own's.") Bug: https://bugzilla.kernel.org/show_bug.cgi?id=216119Acked-by:
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Alex Deucher authored
Was dropped when we converted to the generic helpers. Fixes: 087451f3 ("drm/amdgpu: use generic fb helpers instead of setting up AMD own's.") Acked-by:
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Maíra Canal authored
Some variables from the struct vba_vars_st are not referenced in any other place on the codebase. As they are not used, this commit removes those variables. Signed-off-by:
Maíra Canal <mairacanal@riseup.net> Signed-off-by:
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Maíra Canal authored
The function CalculateBytePerPixelAnd256BBlockSizes was defined four times: on display_mode_vba_30.c, display_rq_dlg_calc_30.c, display_mode_vba_31.c and display_rq_dlg_calc_31.c. In order to avoid code duplication, the CalculateBytePerPixelAnd256BBlockSizes is defined on display_mode_vba_30.h and used across dcn30 and dcn31. Signed-off-by:
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Yang Li authored
Eliminate the follow smatch warning: drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:3151 commit_planes_for_stream() warn: inconsistent indenting Signed-off-by:
Yang Li <yang.lee@linux.alibaba.com> Signed-off-by:
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Maíra Canal authored
The function Calculate256BBlockSizes always returns true, regardless of the parameters. As any file checks the return of the function, this commit changes the return value to void. Signed-off-by:
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André Almeida authored
To avoid code repetition, unify the function exit path when possible. No functional changes. Acked-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
André Almeida <andrealmeid@igalia.com> Signed-off-by:
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Jianglei Nie authored
if amdgpu_mes_ctx_alloc_meta_data() fails, we should call amdgpu_vm_fini() to handle amdgpu_vm_init(). Add a new lable before amdgpu_vm_init() and goto this lable when amdgpu_mes_ctx_alloc_meta_data() fails. Signed-off-by:
Jianglei Nie <niejianglei2021@163.com> Signed-off-by:
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Alvin Lee authored
[Description] Program audio DTO before wall dto for audio Reviewed-by:
Martin Leung <Martin.Leung@amd.com> Acked-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by:
Alvin Lee <Alvin.Lee2@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Aric Cyr authored
This DC patchset brings improvements in multiple areas. In summary, we highlight: - Program ACP-related registers - Fixes for DMUB, DPIA, PSR, and others - Improvements in the pipe split - Add SubVP code - Add basic setup for FAMS support - Improve BB capabilities Acked-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
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Hamza Mahfooz authored
hdmi_frl_pcon_support has been the source of confusion. So, rename it to dp_hdmi21_pcon_support. Signed-off-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Tested-by:
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Hamza Mahfooz authored
Generic PCON SST support already exists and works for newer ASICs. So, enable it by default. Acked-by:
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Chris Park authored
[Why] Integrate OVT timing from DM to DC logic to update info frame and mode management to report the resolution to the OS. [How] Reflect RID and Frame Rate to AVI InfoFrame Version 5. Define new Timing Standard for OVT timing. Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
Alan Liu <HaoPing.Liu@amd.com> Signed-off-by:
Chris Park <Chris.Park@amd.com> Tested-by:
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Jack Xiao authored
MES fw updated to support unmapping legacy gfx/compute queue. Signed-off-by:
Jack Xiao <Jack.Xiao@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Michael Strauss authored
[WHY] lt_settings' pointers remain uninitialized but nonzero if display fails to light up with no DPCD/EDID info populated, leading to a hang on access Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
Michael Strauss <michael.strauss@amd.com> Tested-by:
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Jimmy Kizito authored
[Why] Uninitialized variable causes diag compilation build failure. [How] - Ensure that variable in question is always initialized before being used. - The variable in question is the USB4 DP training pattern. In case an unsupported training pattern has been requested, update status accordingly and abort current link training attempt. Reviewed-by:
Meenakshikumar Somasundaram <Meenakshikumar.Somasundaram@amd.com> Acked-by:
Jimmy Kizito <Jimmy.Kizito@amd.com> Tested-by:
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Harry Wentland authored
Move all linux includes into OS types. Acked-by:
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Eric Bernstein authored
[Why] For some customer blending transition cases, the available pipe for second stream is a pipe index that is greater than the number of timing generators, which can cause a problem in acquire_first_free_pipe since it assumes same index for pipe and timing generator [How] Added logic to use last timing generator index if the pipe index is greater than number of timing generators. Acked-by:
Eric Bernstein <eric.bernstein@amd.com> Tested-by:
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Duncan Ma authored
[Why] Some panels may require more MST delay on discovery [How] Add panel patch and debug mst delay flag Reviewed-by:
Duncan Ma <duncan.ma@amd.com> Tested-by:
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Jimmy Kizito authored
[Why] Some TBT3 docks have DPOAs which report USB4 capability and are expected to support USB4 DPOA features such as FEC/DSC. [How] By default, do not override FEC/DSC capabilities reported by TBT3 docks. Reviewed-by:
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Rodrigo Siqueira authored
Recently we introduced a patch for fixing an MST issue, but it caused a regression on Club 3D since we could not set a refresh rate higher than 60Hz. This commit fixes this issue by adding a proper check after validating the stream. Fixes: f04d275d ("drm/amd/display: add mst port output bw check") Reviewed-by:
Hersen Wu <hersenxs.wu@amd.com> Acked-by:
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Meenakshikumar Somasundaram authored
[Why] DC debug option to configure dpia hpd processing delay is not required. [How] Remove dc debug option for dpia hpd delay and also added log for querying dpia hpd state. Reviewed-by:
Mustapha Ghaddar <Mustapha.Ghaddar@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Chris Park authored
[Why] With ODM policy 2 to 1, there exists a new use case scenario where stream content is unchanged, but ODM may be used. When this happens, the stream needs to be committed with a new pipe setting. This did not happen due to stream change detection logic not accounting for ODM. [How] Set ODM flag in stream and commit stream when change in ODM has been detected due to policy change. Reviewed-by:
Samson Tam <Samson.Tam@amd.com> Acked-by:
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Dmytro Laktyushkin authored
This w/a has a bad interaction with seamless boot toggling an active stream. Most panels recover, however some fail leading to display corruption. Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Tested-by:
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Fangzhi Zuo authored
[Why] Unexpected change of aux hw mapping causes dmub soft hang when initiate aux transation at wrong aux channel. ddc_channel stands for hw dp aux index which is from vbios, but link_index is pure software concept for link count depending on which link is probed first. They are not interchangeable. dmub aux transaction could pass if happens eDP link_index gets the same value as vbios ddc_channel, e.g., ddc_channel = 1, link_index = 1 if they gets different, e.g., ddc_channel = 2, link_index = 0, overwrite ddc_channel with link_index will have wrong ddc channel being used for aux transaction in dmub PSR, cause aux transaction soft hang. [How] ddc_channel mapping to each link is determined by vbios and further parsed in dc. Such info. should not be touched in any kind, otherwise the mapping is screwed up leading to aux transaction timeout. Reviewed-by:
Fangzhi Zuo <Jerry.Zuo@amd.com> Tested-by:
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Nicholas Kazlauskas authored
[Why & How] Check lenc is not NULL since dynamic link encoder assignment could end up assigning a NULL link encoder. Reviewed-by:
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Nicholas Kazlauskas authored
[Why] It's possible that we don't have a link encoder assignment if the context is NULL but we're calling dc_add_stream_to_ctx from DM directly. Link encoder assignment will happen later after global validation runs with fast_validate = false. [How] Remove the ASSERTION. We already guard against NULL link_enc. Reviewed-by:
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Nicholas Kazlauskas authored
[Why] In the case where we don't support DMUB aux but we have DPIA links in the configuration we might try to message AUX using the legacy path - where DDC pin is NULL. This causes a NULL pointer dereference. [How] Guard against NULL DDC pin, return a failure for aux engine acquire. Reviewed-by:
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Alan Liu authored
- Setup the shift and mask of HDMI_ACP_SEND register - Program the register in hdmi stream encoder - Also update ACP register in azalia configuration Reviewed-by:
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Evgenii Krasnikov authored
[HOW/WHY] Add an option to skip edp_wait_for_hpd_ready when necessary Reviewed-by:
Jayendran Ramani <Jayendran.Ramani@amd.com> Acked-by:
Evgenii Krasnikov <Evgenii.Krasnikov@amd.com> Tested-by:
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Alvin Lee authored
[Description] In general cases we want to keep the dram clock change requirement (we prefer configs that support MCLK switch). Only override to false for SubVP. Reviewed-by:
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Jun Lei authored
[why] Some parts are consuming dangerously close to maximum number of states supported when updating the BB (i.e. 8). [how] Change maximum stages from 9 to 20. Acked-by:
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Jimmy Kizito authored
[Why] While applying a state to hardware, there is a transition period where the back-end is reset using the old state; then enabled using the new state. Generally, the link encoder configuration module queries stream-to-encoder assignments in either the new or old state based on a mode variable. During the transition there is a need to query both states, however toggling this mode variable can lead to incorrect programming of encoders. [How] - Add new function to explicity query stream-to-encoder assignment in the current state rather than intermittently switch the mode of operation of the link encoder assignment module. - Add additional checks for encoder assignment defects. - Explicitly reset the mode of operation if application of state to hardware ends prematurely. Acked-by:
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