- 18 Jun, 2023 11 commits
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Konrad Dybcio authored
Since the introduction of A6xx support, we've been enabling the CX GMU power counter 0 in a bit of a weird spot. Move it to hw_init so that GMU wrapper GPUs can reuse the same code paths. As a bonus, this order makes it easier to compare mainline and downstream register access traces. Signed-off-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/542765/Signed-off-by:
Rob Clark <robdclark@chromium.org>
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Konrad Dybcio authored
Rename lower_bit to hbb_lo and explain what it signifies. Add explanations (wherever possible to other tunables). Port setting min_access_length, ubwc_mode and hbb_hi from downstream. Reviewed-by:
Rob Clark <robdclark@gmail.com> Reviewed-by:
Akhil P Oommen <quic_akhilpo@quicinc.com> Signed-off-by:
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Konrad Dybcio authored
Currently we're only deasserting REG_A6XX_RBBM_GBIF_HALT, but we also need REG_A6XX_GBIF_HALT to be set to 0. This is typically done automatically on successful GX collapse, but in case that fails, we should take care of it. Also, add a memory barrier to ensure it's gone through before jumping to further initialization. Reviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by:
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Konrad Dybcio authored
Introduce a6xx_gpu_sw_reset() in preparation for adding GMU wrapper GPUs and reuse it in a6xx_gmu_force_off(). This helper, contrary to the original usage in GMU code paths, adds a readback+delay sequence to ensure that the reset is never deasserted too quickly due to e.g. OoO execution going crazy. Signed-off-by:
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Konrad Dybcio authored
Unify the indentation and explain the cryptic 0xF value. Reviewed-by:
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Konrad Dybcio authored
This function is responsible for telling the GPU to halt transactions on all of its relevant buses, drain them and leave them in a predictable state, so that the GPU can be e.g. reset cleanly. Move the function to a6xx_gpu.c, remove the static keyword and add a prototype in a6xx_gpu.h to accomodate for the move. Reviewed-by:
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Konrad Dybcio authored
As pointed out by Akhil during the review process of GMU wrapper introduction [1], it makes sense to move this write into the function that's responsible for forcibly shutting the GMU off. It is also very convenient to move this to GMU-specific code, so that it does not have to be guarded by an if-condition to avoid calling it on GMU wrapper targets. Move the write to the aforementioned a6xx_gmu_force_off() to achieve that. No effective functional change. [1] https://lore.kernel.org/linux-arm-msm/20230501194022.GA18382@akhilpo-linux.qualcomm.com/Reviewed-by:
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Konrad Dybcio authored
These two will be reused by at least A619_holi in the non-gmu paths. Turn them non-static them to make it possible. Reviewed-by:
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Konrad Dybcio authored
The adreno_is_revn rework came at the same time as A690 introduction and that resulted in it not covering all cases. Fix it. Signed-off-by:
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Konrad Dybcio authored
The "GMU Wrapper" is Qualcomm's name for "let's treat the GPU blocks we'd normally assign to the GMU as if they were a part of the GMU, even though they are not". It's a (good) software representation of the GMU_CX and GMU_GX register spaces within the GPUSS that helps us programatically treat these de-facto GMU-less parts in a way that's very similar to their GMU-equipped cousins, massively saving up on code duplication. The "wrapper" register space was specifically designed to mimic the layout of a real GMU, though it rather obviously does not have the M3 core et al. To sum it all up, the GMU wrapper is essentially a register space within the GPU, which Linux sees as a dumbed-down regular GMU: there's no clocks, interrupts, multiple reg spaces, iommus and OPP. Document it. Reviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
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Konrad Dybcio authored
The "GMU Wrapper" is Qualcomm's name for "let's treat the GPU blocks we'd normally assign to the GMU as if they were a part of the GMU, even though they are not". It's a (good) software representation of the GMU_CX and GMU_GX register spaces within the GPUSS that helps us programatically treat these de-facto GMU-less parts in a way that's very similar to their GMU-equipped cousins, massively saving up on code duplication. The "wrapper" register space was specifically designed to mimic the layout of a real GMU, though it rather obviously does not have the M3 core et al. GMU wrapper-equipped A6xx GPUs require clocks and clock-names to be specified under the GPU node, just like their older cousins. Account for that. Acked-by:
Rob Herring <robh@kernel.org> Reviewed-by:
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- 16 Jun, 2023 5 commits
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Dmitry Baryshkov authored
It makes no sense to pass NULL parameters to dsi_ctrl_config() in the disable case. Split dsi_ctrl_config() into enable and disable parts and drop unused params. Signed-off-by:
Marijn Suijten <marijn.suijten@somainline.org> Patchwork: https://patchwork.freedesktop.org/patch/542559/ Link: https://lore.kernel.org/r/20230614224402.296825-2-dmitry.baryshkov@linaro.org
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Dmitry Baryshkov authored
Several source clocks are not used anymore, so stop handling them. Signed-off-by:
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Dmitry Baryshkov authored
sm6115, sm6375 and qcm2290 do not have INTF_0. Drop corresponding interface definitions. Signed-off-by:
Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by:
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Dmitry Baryshkov authored
Each MERGE_3D block has just two registers. Correct the block length accordingly. Fixes: 4369c93c ("drm/msm/dpu: initial support for merge3D hardware block") Signed-off-by:
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Dmitry Baryshkov authored
During IRQ conversion we have lost the PP_DONE interrupts for sc7280 platform. This was left unnoticed, because this interrupt is only used for CMD outputs and probably no sc7[12]80 systems use DSI CMD panels. Fixes: 667e9985 ("drm/msm/dpu: replace IRQ lookup with the data in hw catalog") Signed-off-by:
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- 15 Jun, 2023 22 commits
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Bjorn Andersson authored
The DP component's unbind operation walks through the submodules to unregister and clean things up. But if the unbind happens because the DP controller itself is being removed, all the memory for those submodules has just been freed. Change the order of these operations to avoid the many use-after-free that otherwise happens in this code path. Fixes: c943b494 ("drm/msm/dp: add displayPort driver support") Signed-off-by:
Bjorn Andersson <quic_bjorande@quicinc.com> Reviewed-by:
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Bjorn Andersson authored
Using devres to depopulate the aux bus made sure that upon a probe deferral the EDP panel device would be destroyed and recreated upon next attempt. But the struct device which the devres is tied to is the DPUs (drm_dev->dev), which may be happen after the DP controller is torn down. Indications of this can be seen in the commonly seen EDID-hexdump full of zeros in the log, or the occasional/rare KASAN fault where the panel's attempt to read the EDID information causes a use after free on DP resources. It's tempting to move the devres to the DP controller's struct device, but the resources used by the device(s) on the aux bus are explicitly torn down in the error path. The KASAN-reported use-after-free also remains, as the DP aux "module" explicitly frees its devres-allocated memory in this code path. As such, explicitly depopulate the aux bus in the error path, and in the component unbind path, to avoid these issues. Fixes: 2b57f726 ("drm/msm/dp: fix aux-bus EP lifetime") Signed-off-by:
Douglas Anderson <dianders@chromium.org> Patchwork: https://patchwork.freedesktop.org/patch/542163/ Link: https://lore.kernel.org/r/20230612220106.1884039-1-quic_bjorande@quicinc.comSigned-off-by:
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Dmitry Baryshkov authored
Since commit 93e81e38 ("drm/fb_helper: Minimize damage-helper overhead") the drm_fb_helper_funcs::fb_dirty helper is required for proper dirty/damage processing. The drm/msm driver requires that to function to let CMD panels to work. Use simplified version of drm_fbdev_generic_helper_fb_dirty() to fix support for CMD mode panels. Reported-by:
Degdag Mohamed <degdagmohamed@gmail.com> Fixes: 93e81e38 ("drm/fb_helper: Minimize damage-helper overhead") Cc: Thomas Zimmermann <tzimmermann@suse.de> Signed-off-by:
Thomas Zimmermann <tzimmermann@suse.de> Reviewed-by:
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Jessica Zhang authored
Currently, slice_count is being used to calculate word count and pkt_per_line. Instead, these values should be calculated using slice per packet, which is not the same as slice_count. Slice count represents the number of slices per interface, and its value will not always match that of slice per packet. For example, it is possible to have cases where there are multiple slices per interface but the panel specifies only one slice per packet. Thus, use the default value of one slice per packet and remove slice_count from the aforementioned calculations. Fixes: 08802f51 ("drm/msm/dsi: Add support for DSC configuration") Fixes: bc6b6ff8 ("drm/msm/dsi: Use DSC slice(s) packet size to compute word count") Reviewed-by:
Jessica Zhang <quic_jesszhan@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/541965/ Link: https://lore.kernel.org/r/20230405-add-dsc-support-v6-5-95eab864d1b6@quicinc.comSigned-off-by:
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Jessica Zhang authored
Add a DPU INTF op to set the DCE_DATA_COMPRESS bit to enable the DCE/DSC 1.2 datapath Note: For now, this op is called for command mode encoders only. Changes to set DATA_COMPRESS for video mode encoders will be posted along with DSC v1.2 support for DP. Signed-off-by:
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Jessica Zhang authored
In DPU 7.x and later, DSC/DCE enablement registers have been moved from PINGPONG to INTF. Thus, add a DPU_INTF_DATA_COMPRESS feature flag that will be set if the DATA_COMPRESS register is in the INTF block. Reviewed-by:
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Jessica Zhang authored
Adjust the pclk rate to divide hdisplay by the compression ratio when DSC is enabled. Signed-off-by:
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Jessica Zhang authored
Currently, when compression is enabled, hdisplay is reduced via integer division. This causes issues for modes where the original hdisplay is not a multiple of 3. To fix this, use DIV_ROUND_UP to divide hdisplay. Suggested-by:
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Abhinav Kumar authored
Add DSC 1.2 hardware blocks to the catalog with necessary sub-block and feature flag information. Each display compression engine (DCE) contains dual DSC encoders so both share same base address but with its own different sub block address. changes in v4: -- delete DPU_DSC_HW_REV_1_1 -- re arrange sc8280xp_dsc[] changes in v4: -- fix checkpatch warning changes in v10: -- remove hard slice from commit text -- replace DPU_DSC_NATIVE_422_EN with DPU_DSC_NATIVE_42x_EN -- change DSC_BLK_1_2 .len from 0x100 to 0x29c changes in v11: -- remove comment at DSC_BLK_1_2 marco Signed-off-by:
Kuogee Hsieh <quic_khsieh@quicinc.com> Reviewed-by:
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Kuogee Hsieh authored
Add support for DSC 1.2 by providing the necessary hooks to program the DPU DSC 1.2 encoder. Changes in v3: -- fixed kernel test rebot report that "__iomem *off" is declared but not used at dpu_hw_dsc_config_1_2() -- unrolling thresh loops Changes in v4: -- delete DPU_DSC_HW_REV_1_1 -- delete off and used real register name directly Changes in v7: -- replace offset with sblk->enc.base -- replace ss with slice Changes in v8: -- fixed checkpatch warning Changes in v9: -- replaced __dsc_calc_ob_max_addr() with __dsc_calc_output_buf_max_addr() -- replaced variable num_ss with num_softslice -- remove inline from function declaration changes in v10: -- rewording text of changes in v9 -- replace DPU_DSC_NATIVE_422_EN with DPU_DSC_NATIVE_42x_EN -- replace drm_dsc_calculate_flatness_det_thresh() with drm_dsc_flatness_det_thresh() Signed-off-by:
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Jessica Zhang authored
Currently, hdisplay is being divided by 3 for DSC. However, this calculation only works for cases where BPP = 8. Update hdisplay calculation to be bytes_per_line / 3, so that it accounts for cases where BPP != 8. Reviewed-by:
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Jessica Zhang authored
Use MSM and DRM DSC helper methods to configure DSC for DSI. Reviewed-by:
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Jessica Zhang authored
Correct the math for slice_last_group_size so that it matches the calculations downstream. Fixes: c110cfd1 ("drm/msm/disp/dpu1: Add support for DSC") Reviewed-by:
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Jessica Zhang authored
The current dpu_hw_dsc calculation for det_thresh_flatness does not match the downstream calculation or the DSC spec. Use the DRM DSC helper for det_thresh_flatness to match downstream implementation and the DSC spec. Fixes: c110cfd1 ("drm/msm/disp/dpu1: Add support for DSC") Reviewed-by:
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Jessica Zhang authored
Introduce MSM-specific DSC helper methods, as some calculations are common between DP and DSC. Reviewed-by:
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Dmitry Baryshkov authored
Use new DRM DSC helpers to setup DSI DSC configuration. The initial_scale_value needs to be adjusted according to the standard, but this is a separate change. Signed-off-by:
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Jessica Zhang authored
Add helper to get the integer value of drm_dsc_config.bits_per_pixel Reviewed-by:
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Dmitry Baryshkov authored
Add a helper setting config values which are typically constant across operating modes (table E-4 of the standard) and mux_word_size (which is a const according to 3.5.2). Signed-off-by:
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Jessica Zhang authored
Add helpers to calculate det_thresh_flatness and initial_scale_value as these calculations are defined within the DSC spec. Reviewed-by:
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Dmitry Baryshkov authored
Add definitions of DSPP blocks present on the sdm845 platform. This should enable color-management on sdm845-bassed devices. Signed-off-by:
Sumit Semwal <sumit.semwal@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/542142/ Link: https://lore.kernel.org/r/20230612182534.3345805-2-dmitry.baryshkov@linaro.org
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Dmitry Baryshkov authored
We can not support color management without DSPP blocks being provided in the HW catalog. Do not enable color management for CRTCs if num_dspps is 0. Fixes: 4259ff7a ("drm/msm/dpu: add support for pcc color block in dpu driver") Reported-by:
Yongqin Liu <yongqin.liu@linaro.org> Signed-off-by:
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Dmitry Baryshkov authored
Change adreno_is_a690() prototype to accept the const struct adreno_gpu pointer instead of a non-const one. This fixes the following warning: In file included from drivers/gpu/drm/msm/msm_drv.c:33: drivers/gpu/drm/msm/adreno/adreno_gpu.h: In function ‘adreno_is_a660_family’: drivers/gpu/drm/msm/adreno/adreno_gpu.h:303:54: warning: passing argument 1 of ‘adreno_is_a690’ discards ‘const’ qualifier from pointer target type [-Wdiscarded-qualifiers] 303 | return adreno_is_a660(gpu) || adreno_is_a690(gpu) || adreno_is_7c3(gpu); Fixes: 1b90e8f8 ("drm/msm/adreno: change adreno_is_* functions to accept const argument") Signed-off-by:
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- 12 Jun, 2023 1 commit
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git://anongit.freedesktop.org/drm/drmDmitry Baryshkov authored
Merge the drm-next tree to pick up the DRM DSC helpers (merged via drm-intel-next tree). MSM DSC v1.2 patches depend on these helpers. Signed-off-by:
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- 10 Jun, 2023 1 commit
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Dmitry Baryshkov authored
All adreno_is_*() functions do not modify their argument in any way, so they can be changed to accept const struct adreno_gpu pointer. Suggested-by:
Stephen Boyd <swboyd@chromium.org> Signed-off-by:
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