- 10 Oct, 2007 6 commits
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Grant Likely authored
Adds the of_platform bus binding to the xilinxfb driver. Needed to use framebuffer devices described in the OF device tree (used by arch/powerpc). Signed-off-by:
Grant Likely <grant.likely@secretlab.ca> Acked-by:
Andrei Konovalov <akonovalov@ru.mvista.com>
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Grant Likely authored
Change the platform bus binding to make use of the established platform_bus API. Signed-off-by:
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Grant Likely authored
Split the device setup code away from the platform bus binding. This is in preparation for adding the of_platform bus binding to this driver and most of the setup code is common between the two busses. Signed-off-by:
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Grant Likely authored
Labels and gotos are used in xilinxfb_assign to unwind allocations on device registration failures. Rename the labels to reflect the error which occured. This change is being made to make it easier to add new failout paths (which occurs in a subsuquent patch) and to make reviewing the failout path easier. Signed-off-by:
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Grant Likely authored
The dev_dbg, dev_err, etc functions provide more context that plain vanilla printk which is useful for debugging. Where appropriate, change printk calls to the appropriate dev_*() call. Signed-off-by:
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Grant Likely authored
Debug support: when DEBUG is defined, output relevant details to the log about the framebuffer registration. Signed-off-by:
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- 08 Oct, 2007 20 commits
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Grant Likely authored
DTC now supports "foo","bar" format for lists of strings; use the new format on the lite5200 device trees. Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Peter Korsgaard authored
On non-QE processors (mpc831x/mpc834x) the SPI clock is the SoC clock. Signed-off-by:
Peter Korsgaard <jacmet@sunsite.dk> Signed-off-by:
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Anton Vorontsov authored
Apart from that the current code doesn't compile it's also meaningless with regard to the MPC8568E-MDS' BCSR. This patch used to reset UCCs properly. Signed-off-by:
Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by:
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Anton Vorontsov authored
1. UCC1's RX_DV pin is 16, not 15; 2. UCC1's phy is at 0x7, not 0x1. Schematics says 0x7, and recent u-boot also using 0x7. 3. Use gianfar's (eTSEC) mdio bus. This is hardware default setup. 4. tx-clock should be CLK16 (GE125, PB31); 5. phy-connection-type is RGMII-ID; Signed-off-by:
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Anton Vorontsov authored
8 bytes padding required to match MPC85xx registers layout. Signed-off-by:
Kim Phillips <kim.phillips@freescale.com> Signed-off-by:
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Anton Vorontsov authored
set_irq_chained_handler overwrites MPIC's handle_irq function (handle_fasteoi_irq) thus MPIC never gets eoi event from the cascaded IRQ. This situation hangs MPIC on MPC8568E. To solve this problem efficiently, QEIC needs pluggable handlers, specific to the underlaying interrupt controller. Patch extends qe_ic_init() function to accept low and high interrupt handlers. To avoid #ifdefs, stack of interrupt handlers specified in the header file and functions are marked 'static inline', thus handlers are compiled-in only if actually used (in the board file). Another option would be to lookup for parent controller and automatically detect handlers (will waste text size because of never used handlers, so this option abolished). qe_ic_init() also changed in regard to support multiplexed high/low lines as found in MPC8568E-MDS, plus qe_ic_cascade_muxed_mpic() handler implemented appropriately. Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by:
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Anton Vorontsov authored
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Timur Tabi authored
Update the definition of the global utilities structure (ccsr_guts) in immap_86xx.h and add some related macros for the Freescale 8610 SOC. Signed-off-by:
Timur Tabi <timur@freescale.com> Signed-off-by:
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Kumar Gala authored
On the majority of 85xx & 86xx we have a register that's ability to assert HRESET_REQ to reset the board. We refactored that code so it can be shared between both platforms into fsl_soc.c and removed all the duplication in each platform directory. Signed-off-by: -
Kumar Gala authored
On the Freescale embedded (83xx, 85xx, 86xx) and a few of the discrete bridges (mpc10x, tsi108) use the new for_each_compatible_node() or for_each_node_by_type() to provide more exact matching when looking for PHBs in the device tree. With the previous code it was possible to match on pci bridges since we were only matching on device_type. Signed-off-by: -
Kumar Gala authored
The LTSSM register is actual 32-bits wide so we should be doing a dword access. Signed-off-by: -
Dale Farnsworth authored
The CONFIG_FSL_BOOKE mmu setup code fails when CONFIG_HIGHMEM=y and the 3 fixed TLB entries cannot exactly map the lowmem size. Each TLB entry can map 4MB, 16MB, 64MB or 256MB, so the failure is observed when the kernel lowmem size is not equal to the sum of up to 3 of those values. Normally, memory is sized in nice numbers, but I observed this problem while testing a crash dump kernel. The failure can also be observed by artificially reducing the kernel's main memory via the mem= kernel command line parameter. This commit fixes the problem by setting __initial_memory_limit in adjust_total_lowmem(). Signed-off-by:
Dale Farnsworth <dale@farnsworth.org> Signed-off-by:
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Xianghua Xiao authored
Add basic board support for the MPC8610 HPCD. This does not include any support the SoC Display or Audio controllers. Signed-off-by:
Xianghua Xiao <x.xiao@freescale.com> Signed-off-by:
Jason Jin <Jason.jin@freescale.com> Signed-off-by:
Jon Loelier <jdl@freescale.com> Signed-off-by:
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Jason Jin authored
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Xianghua Xiao authored
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Peter Korsgaard authored
Mode should be "cpu-qe" for QE in CPU mode. "qe" should be reserved for native QE mode. Signed-off-by:
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Peter Korsgaard authored
According to booting-without-of.txt, compatible should be "fsl_spi" and mode "cpu" or "qe" for the fsl SPI controllers. Signed-off-by:
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Timur Tabi authored
This patch makes numerous miscellaneous code improvements to the QE library. 1. Remove struct ucc_common and merge ucc_init_guemr() into ucc_set_type() (every caller of ucc_init_guemr() also calls ucc_set_type()). Modify all callers of ucc_set_type() accordingly. 2. Remove the unused enum ucc_pram_initial_offset. 3. Refactor qe_setbrg(), also implement work-around for errata QE_General4. 4. Several printk() calls were missing the terminating \n. 5. Add __iomem where needed, and change u16 to __be16 and u32 to __be32 where appropriate. 6. In ucc_slow_init() the RBASE and TBASE registers in the PRAM were programmed with the wrong value. 7. Add the protocol type to struct us_info and updated ucc_slow_init() to use it, instead of always programming QE_CR_PROTOCOL_UNSPECIFIED. 8. Rename ucc_slow_restart_x() to ucc_slow_restart_tx() 9. Add several macros in qe.h (mostly for slow UCC support, but also to standardize some naming convention) and remove several unused macros. 10. Update ucc_geth.c to use the new macros. 11. Add ucc_slow_info.protocol to specify which QE_CR_PROTOCOL_xxx protcol to use when initializing the UCC in ucc_slow_init(). 12. Rename ucc_slow_pram.rfcr to rbmr and ucc_slow_pram.tfcr to tbmr, since these are the real names of the registers. 13. Use the setbits, clrbits, and clrsetbits where appropriate. 14. Refactor ucc_set_qe_mux_rxtx(). 15. Remove all instances of 'volatile'. 16. Simplify get_cmxucr_reg(); 17. Replace qe_mux.cmxucrX with qe_mux.cmxucr[]. 18. Updated struct ucc_geth because struct ucc_fast is not padded any more. Signed-off-by: -
Kumar Gala authored
We now generate vdso[32,64].so.dbg as part of the build so add them to .gitignore Signed-off-by: -
Kumar Gala authored
The PCI nodes on the MPC8568 dts didn't get moved up to be sibilings of the SOC node when we did that clean up for some reason. Fix that up and some minor whitespace and adjusting the size of the soc reg property. Signed-off-by:
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- 04 Oct, 2007 14 commits
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Anton Vorontsov authored
According to u-boot/board/mpc8568mds/init.S: LAW(Local Access Window) configuration: 2) 0xa000_0000 0xbfff_ffff PCIe MEM 512MB 4) 0xe280_0000 0xe2ff_ffff PCIe I/O 8M Signed-off-by:
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Anton Vorontsov authored
MPC8568E-MDS have DS1374 chip on the I2C bus, thus let's use it. This patch also adds #address-cells and #size-cells to the I2C controllers nodes. p.s. DS1374 rtc class driver is in the -mm tree, its name is rtc-rtc-class-driver-for-the-ds1374.patch. Signed-off-by:
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Anton Vorontsov authored
i2c_board_info used semi-initialized, causing garbage in the info->flags, and that, in turn, causes various symptoms of i2c malfunctioning, like PEC mismatches. Signed-off-by:
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Scott Wood authored
The way the current CPM binding describes available multi-user (a.k.a. dual-ported) RAM doesn't work well when there are multiple free regions, and it doesn't work at all if the region doesn't begin at the start of the muram area (as the hardware needs to be programmed with offsets into this area). The latter situation can happen with SMC UARTs on CPM2, as its parameter RAM is relocatable, u-boot puts it at zero, and the kernel doesn't support moving it. It is now described with a muram node, similar to QE. The current CPM binding is sufficiently recent (i.e. never appeared in an official release) that compatibility with existing device trees is not an issue. The code supporting the new binding is shared between cpm1 and cpm2, rather than remain separated. QE should be able to use this code as well, once minor fixes are made to its device trees. Signed-off-by:
Scott Wood <scottwood@freescale.com> Signed-off-by:
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Kumar Gala authored
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Emil Medve authored
According to the publicly available MPC8360E RM (rev. 1 from 09/2006 and rev. 2 from 05/2007) and MPC8323E RM (rev. 1 from 09/2006), CEURNR is the QE microcode revision number register and is located at offset 0x1b8 within the QE internal register space Signed-off-by:
Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by:
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Peter Korsgaard authored
Add support for the I2C devices handled by the rtc-ds1307 driver to of_register_i2c_devices. Cc: G. Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by:
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Peter Korsgaard authored
Fix a trivial printk typo in fsl_soc. Cc: G. Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by:
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Scott Wood authored
Previously, Soft_emulate_8xx was called with no implementation, resulting in build failures whenever building 8xx without math emulation. The implementation is copied from arch/ppc to resolve this issue. However, this sort of minimal emulation is not a very good idea other than for compatibility with existing userspaces, as it's less efficient than soft-float and can mislead users into believing they have soft-float. Thus, it is made a configurable option, off by default. Signed-off-by:
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Roy Zang authored
This patch adds cuboot support for MPC7448HPC2 platform. The cuImage can be used with legacy u-boot without FDT support. Signed-off-by:
Roy Zang <tie-fei.zang@freescale.com> Acked-by:
David Gibson <david@gibson.dropbear.id.au> Signed-off-by:
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Scott Wood authored
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Scott Wood authored
1. PCI and reset are factored out into pq2.c. I renamed them from m82xx to pq2 because they won't work on the Integrated Host Processor line of 82xx chips (i.e. 8240, 8245, and such). 2. The PCI PIC, which is nominally board-specific, is used on multiple boards, and thus is used into pq2ads-pci-pic.c. 3. The new CPM binding is used. 4. General cleanup. Signed-off-by:
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Scott Wood authored
This board is also resold by Freescale under the names "QUICCStart MPC885 Evaluation System" and "CWH-PPC-885XN-VE". Signed-off-by:
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Scott Wood authored
It now uses the new CPM binding and the generic pin/clock functions, and has assorted fixes and cleanup. Signed-off-by:
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