- 13 Jun, 2018 13 commits
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Evan Quan authored
Gfxoff is already enabled in amdgpu_device_ip_set_powergating_state. So, no need to enable it again in pp_late_init. Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Evan Quan authored
WARN_ON possible buffer overflow and avoid unnecessary dereference. v2: change BUG_ON to WARN_ON Signed-off-by:
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Shaoyun Liu authored
The register field hsas been changed in df 3.6, update to correct setting Signed-off-by:
Shaoyun Liu <Shaoyun.Liu@amd.com> Acked-by:
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Rex Zhu authored
As hw required, soc clock must large than mclk, So we set max soc clock to OD Max Memory clk. But on workstation, vbios do not support OD feature, the OD max memory clock is equal to 0. In this case, driver can support underclocking. and set od max memory clock to the value in highest memory dpm level. So the od max memory clock should be less than highest soc clock. and driver should not change the soc clock. caused by commit ca57b9b0a156 ("drm/amd/pp: Allow underclocking when od table is empty in vbios") Reviewed-by:Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
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Pratik Vishwakarma authored
Fixes stale buffer object (bo) usage for cursor plane Cursor plane's bo operations are handled in DC code. Currently, atomic_commit() does not handle bo operations for cursor plane, as a result the bo assigned for cursor plane in dm_plane_helper_prepare_fb() is not coherent with the updates to the same made in dc code.This mismatch leads to "bo" corruption and hence crashes during S3 entry. This patch cleans up the code which was added as a hack for 4.9 version only. Reviewed-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by:
Pratik Vishwakarma <Pratik.Vishwakarma@amd.com> Signed-off-by:
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Colin Ian King authored
The current use of result is or'ing in values and checking for a non-zero result, however, result is not initialized to zero so it potentially contains garbage to start with. Fix this by initializing it to the first return from the call to vega10_program_didt_config_registers. Detected by cppcheck: "(error) Uninitialized variable: result" Fixes: 9b7b8154 ("drm/amd/powerplay: added didt support for vega10") Signed-off-by:
Colin Ian King <colin.king@canonical.com> Acked-by:
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Evan Quan authored
The clocks should be adjusted after display configuration changed. Otherwise, the socclk and memclk may be forced on an unnecessary higher level. Signed-off-by:
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Lyude Paul authored
So, unfortunately I recently made the discovery that in the upstream kernel, the only reason that amdgpu is not currently suffering from issues with runtime PM putting the GPU into suspend while it's driving displays is due to the fact that on most prime systems, we have sound devices associated with the GPU that hold their own runtime PM ref for the GPU. What this means however, is that in the event that there isn't any kind of sound device active (which can easily be reproduced by building a kernel with sound drivers disabled), the GPU will fall asleep even when there's displays active. This appears to be in part due to the fact that amdgpu has not actually ever relied on it's rpm_idle() function to be the only thing keeping it running, and normally grabs it's own power references whenever there are displays active (as can be seen with the original pre-DC codepath in amdgpu_display_crtc_set_config() in amdgpu_display.c). This means it's very likely that this bug was introduced during the switch over the DC. So to fix this, we start grabbing runtime PM references every time we enable a previously disabled CRTC in atomic_commit_tail(). This appears to be the correct solution, as it matches up with what i915 does in i915/intel_runtime_pm.c. The one sideaffect of this is that we ignore the variable that the pre-DC code used to use for tracking when it needed runtime PM refs, adev->have_disp_power_ref. This is mainly because there's no way for a driver to tell whether or not all of it's CRTCs are enabled or disabled when we've begun committing an atomic state, as there may be CRTC commits happening in parallel that aren't contained within the atomic state being committed. So, it's safer to just get/put a reference for each CRTC being enabled or disabled in the new atomic state. Signed-off-by:
Lyude Paul <lyude@redhat.com> Acked-by: Christian König <christian.koenig@amd.com>. Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Huang Rui authored
Patch 9667849b: "drm/amd/powerplay: add control gfxoff enabling in late init" from Mar 13, 2018, leads to the following static checker warning: drivers/gpu/drm/amd/amdgpu/../powerplay/amd_powerplay.c:194 pp_late_init() error: we previously assumed 'hwmgr' could be null (see line 185) drivers/gpu/drm/amd/amdgpu/../powerplay/amd_powerplay.c This patch fixes the warning to add hwmgr checking. Reported-by:
Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
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Huang Rui authored
After defer the execution of clockgating enabling, at that time, gfx already enter into "off" state. Howerver, clockgating enabling will use MMIO to access the gfx registers, then get the gfx hung. So here we should move the gfx powergating and gfxoff enabling behavior at the end of initialization behind clockgating. Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Cc: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Junwei Zhang authored
v2: assign bo_va as well We need to put the lose ends on the invalid list because it is possible that we need to split up huge pages for them. Cc: stable@vger.kernel.org Signed-off-by:
David Zhou <david1.zhou@amd.com> Signed-off-by:
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Huang Rui authored
The sos ucode version will be changed to align with the value of mmMP0_SMN_C2PMSG_58. Then we add a checking for this. Meanwhile, we have to be compatibility backwards. So it adds serveral recent legacy versions as the white list for the version checking. Signed-off-by:
Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by:
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Huang Rui authored
It missed vcn.fw_version setting when init vcn microcode, and it will be used to report vcn ucode version via amdgpu_firmware_info sysfs interface. Signed-off-by:
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- 01 Jun, 2018 2 commits
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Alex Deucher authored
This reverts commit 13b40935. This was a workaround for a bug in the HDA driver that prevented the HDA audio chip from going into runtime pm which prevented the GPU from going into runtime pm. Bug: https://bugs.freedesktop.org/show_bug.cgi?id=106597Reviewed-by:
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Colin Ian King authored
The comparison with the number of elements in array df_v3_7_channel_number is off-by-one and can produce an array out-of-bounds read if fb_channel_number is equal to the number of elements of the array. Fix this by changing the comparison to >= instead of >. Detected by CoverityScan, CID#1469489 ("Out-of-bounds read") Fixes: 13b58150 ("drm/amdgpu/df: implement df v3_6 callback functions (v2)") Signed-off-by:
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- 31 May, 2018 3 commits
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Shaoyun Liu authored
When PP block is disabled, return a fix value(100M) for mclk and sclk on bare-metal mode. This will cover the emulation mode as well. Signed-off-by:
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Feifei Xu authored
Update mmCB_DCC_CONFIG register goldensetting. Signed-off-by:
Feifei Xu <Feifei.Xu@amd.com> Reviewed-by:
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Rex Zhu authored
if max od engine clock limit and memory clock limit are not set in vbios. driver will allow underclocking instand of disable od feature completely. Reviewed-by:
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- 30 May, 2018 7 commits
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Alex Deucher authored
Fixes a crash on asics without powerplay yet (e.g., vega20). Reviewed-by: Rex Zhu<rezhu@amd.com> Signed-off-by: -
Mikita Lipski authored
Get rid of an empty dublicate of smu10_display_clock_voltage_request Add display_clock_voltage_request to smu10 functions struct so it can be called from outside the class and connect the pointer to the function. That way Display driver can finally apply clock voltage requests when needed. Signed-off-by:
Mikita Lipski <mikita.lipski@amd.com> Reviewed-by:
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Evan Quan authored
The AMD_CG_SUPPORT_HDP_LS was wrongly written as AMD_CG_SUPPORT_BIF_LS. Signed-off-by:
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Evan Quan authored
The .syspll_id and .dfsdid are not initialzed correctly. And le32_to_cpu transfer is needed on the output. Signed-off-by:
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Evan Quan authored
The SMU11 SYSPLL0 clock ids were assigned wrong values. Signed-off-by:
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Chunming Zhou authored
In per-vm-bo case, there could be no bo list. But gds bo created from user space must be passed to bo list. So adding a check to prevent to creat gds bo as per-vm-bo. Signed-off-by:
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Emily Deng authored
As now enabled per vm bo feature, the user mode driver won't supply the bo_list generally, for this case, the gdb_base, gds_size, gws_base, gws_size and oa_base, oa_size won't be set. v2: fix warning (Chunming) Signed-off-by:
Emily Deng <Emily.Deng@amd.com> Reviewed-by:
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- 29 May, 2018 15 commits
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Leo (Sunpeng) Li authored
For cases where the CRTC is inactive (DPMS off), where a modeset is not required, yet the CRTC is still in the atomic state, we should not attempt to update anything on it. Previously, we were relying on the modereset_required() helper to check the above condition. However, the function returns false immediately if a modeset is not required, ignoring the CRTC's enable/active state flags. The correct way to filter is by looking at these flags instead. Fixes: e277adc5 "drm/amd/display: Hookup color management functions" Bugzilla: https://bugs.freedesktop.org/106194Signed-off-by:
Leo (Sunpeng) Li <sunpeng.li@amd.com> Reviewed-by:
Michel Dänzer <michel.daenzer@amd.com> Signed-off-by:
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Nikola Cornij authored
DP 1.4 compliance now requires that registers at DP_SINK_COUNT_ESI range (0x2002-0x2003, 0x200c-0x200f) are read instead of DP_SINK_COUNT range (0x200-0x2005. Signed-off-by:
Nikola Cornij <nikola.cornij@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Nikola Cornij authored
DP 1.4 compliance requires 16 bytes to be read when reading link caps, i.e. it requires DP_ADAPTER_CAP to be included. Included it for all DP versions because reading more than required won't fail. Signed-off-by:
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Mikita Lipski authored
Prevent interrupt programming of a crtc on which the stream is disabled and it doesn't have an OTG to reference. Signed-off-by:
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Dmytro Laktyushkin authored
This change will fix wb and display scaling when ratios of 4 or more are involved Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
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Leo (Sunpeng) Li authored
When a DRM mode reset is called on resume, the connector state's destructor is not called. This leaves a dangling reference on the CRTC commit object, which was obtained by the connector state during commit setup. Signed-off-by:
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Eric Bernstein authored
Add register programming to support TMZ and DCC on secondary surfaces. Signed-off-by:
Eric Bernstein <eric.bernstein@amd.com> Reviewed-by:
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Eric Bernstein authored
Add register programming to support 16bpc component depth for DP. Signed-off-by:
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Roman Li authored
Fixing warning on dce10 with HDMI display. Signed-off-by:
Roman Li <Roman.Li@amd.com> Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Reviewed-by:
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Charlene Liu authored
Signed-off-by:
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Mikita Lipski authored
If connector doesn't have a sink, fake sink is created, but never released as it assumed that its destroyed with the stream it is used for. But now sink is released before the stream maintaing refcount consistency. This way we also avoid assigning anything to connector keeping all the operation local. Signed-off-by:
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Roman Li authored
FBC enabling and disabling path has msleep which leads to BUG hit when called in atomic context, hence this patch replaces msleeps with udelays appropriately. Signed-off-by:
Shirish S <shirish.s@amd.com> Signed-off-by:
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Mikita Lipski authored
Delete if statement that would force any display's color depth higher than 8 bpc to 8 Signed-off-by:
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Leo Liu authored
It should be stateless, and no need for scheduler to take care specially. Signed-off-by:
Leo Liu <leo.liu@amd.com> Reviewed-by:
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Deepak Sharma authored
Move logic of getting supported domain to a helper function Signed-off-by:
Deepak Sharma <Deepak.Sharma@amd.com> Reviewed-by:
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