- 27 Jul, 2020 2 commits
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Konrad Dybcio authored
Add missing halt_check, hwcg_reg and hwcg_bit properties. These were likely omitted when porting the driver upstream. Signed-off-by:
Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200726111215.22361-9-konradybcio@gmail.com Fixes: f2a76a29 ("clk: qcom: Add Global Clock controller (GCC) driver for SDM660") Signed-off-by:
Stephen Boyd <sboyd@kernel.org>
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Konrad Dybcio authored
This will be required in order to support the modem upstream. Signed-off-by:
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- 24 Jul, 2020 16 commits
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Taniya Das authored
The Low Power Audio subsystem clocks are required for Audio client to be able to request for the clocks and power domains. Signed-off-by:
Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/1595606878-2664-5-git-send-email-tdas@codeaurora.org [sboyd@kernel.org: Drop unused ret in probe function] Signed-off-by:
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Taniya Das authored
Add the GCC lpass clock which is required to access the LPASS core clocks. Signed-off-by:
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Taniya Das authored
The LPASS(Low Power Audio Subsystem) clock provider have a bunch of generic properties that are needed in a device tree. Also add clock ids for GCC LPASS and LPASS Core clock IDs for LPASS client to request for the clocks. Signed-off-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/1595606878-2664-3-git-send-email-tdas@codeaurora.orgSigned-off-by:
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Taniya Das authored
Add support for the RETAIN_FF_ENABLE feature which enables the usage of retention registers. These registers maintain their state after disabling and re-enabling a GDSC. Signed-off-by:
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Stephen Boyd authored
A clk driver can be a module but the gdsc code is in the common module. Export this symbol so that allmodconfig builds keep working. Cc: Jonathan Marek <jonathan@marek.ca> Fixes: 0638226d ("clk: qcom: add common gdsc_gx_do_nothing_enable for gpucc drivers") Signed-off-by:
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Jonathan Marek authored
Add support for the graphics clock controller found on SM8250 based devices. This is initially copied from the downstream kernel, but has been modified to more closely match the upstream sc7180 driver. Signed-off-by:
Jonathan Marek <jonathan@marek.ca> Tested-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20200709135251.643-12-jonathan@marek.caSigned-off-by:
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Jonathan Marek authored
Add support for the graphics clock controller found on SM8150 based devices. This is initially copied from the downstream kernel, but has been modified to more closely match the upstream sc7180 driver. Signed-off-by:
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Jonathan Marek authored
All gpucc drivers need this, so move it to common code instead of duplicating it in every gpucc driver. Signed-off-by:
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Jonathan Marek authored
Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's SM8250 SoCs. Signed-off-by:
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Jonathan Marek authored
Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's SM8150 SoCs. Signed-off-by:
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Jonathan Marek authored
These two bindings are almost identical, so combine them into one. This will make it easier to add the sm8150 and sm8250 gpucc bindings. Signed-off-by:
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Jonathan Marek authored
The fixed alpha pll ops only use it for clamping in round_rate, which is unnecessary. This is consistent with SM8250 GCC not using vco_table. Signed-off-by:
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Jonathan Marek authored
Lucid PCAL_DONE is different from trion. Signed-off-by:
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Jonathan Marek authored
Fixed ops were already identical, this adds support for non-fixed ops by sharing between trion and lucid. This also changes the names for trion ops to be consistent with the rest. Note LUCID_PCAL_DONE is renamed to TRION_PCAL_DONE because it is wrong for lucid, LUCID_PCAL_DONE should be BIT(27). Next patch will address this. Signed-off-by:
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Jonathan Marek authored
0x44 isn't a register offset, it is the value that goes into CAL_L_VAL. Fixes: 548a9095 ("clk: qcom: clk-alpha-pll: Add support for Trion PLLs") Signed-off-by:
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Jonathan Marek authored
Fix the parents and set BRANCH_HALT_SKIP. From the downstream driver it should be a 500us delay and not skip, however this matches what was done for other clocks that had 500us delay in downstream. Fixes: f73a4230 ("clk: qcom: gcc: Add GPU and NPU clocks for SM8150") Signed-off-by:
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- 23 Jul, 2020 1 commit
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Loic Poulain authored
Fix errors reported by dt_binding_check. - Fix literal block scalar for dts example - Fix schema identifier URI Signed-off-by:
Loic Poulain <loic.poulain@linaro.org> Link: https://lore.kernel.org/r/1595326714-20485-1-git-send-email-loic.poulain@linaro.orgReviewed-by:
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- 21 Jul, 2020 4 commits
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Taniya Das authored
The display gpll0 branch clock inside GCC needs to always be enabled. Otherwise the AHB clk (disp_cc_mdss_ahb_clk_src) for the display clk controller (dispcc) will stop clocking while sourcing from gpll0 when this branch inside GCC is turned off during unused clk disabling. We can never turn this branch off because the AHB clk for the display subsystem is needed to read/write any registers inside the display subsystem including clk related ones. This makes this branch a really easy way to turn off AHB access to the display subsystem and cause all sorts of mayhem. Let's just make the clk ops keep the clk enabled forever and ignore any attempts to disable this clk so that dispcc accesses keep working. Signed-off-by:
Evan Green <evgreen@chromium.org> Link: https://lore.kernel.org/r/1594796050-14511-1-git-send-email-tdas@codeaurora.org Fixes: 17269568 ("clk: qcom: Add Global Clock controller (GCC) driver for SC7180") Fixes: 06391edd ("clk: qcom: Add Global Clock controller (GCC) driver for SDM845") [sboyd@kernel.org: Fill out commit text more] Signed-off-by:
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Ansuel Smith authored
Add support for child probing needed for tsens driver that share the same regs of gcc for this platform. Signed-off-by:
Ansuel Smith <ansuelsmth@gmail.com> Reviewed-by:
Amit Kucheria <amit.kucheria@linaro.org> Link: https://lore.kernel.org/r/20200716022817.30439-2-ansuelsmth@gmail.comSigned-off-by:
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Wei Yongjun authored
The sparse tool complains as follows: drivers/clk/qcom/clk-cpu-8996.c:341:19: warning: symbol 'cpu_msm8996_clks' was not declared. Should it be static? This variable is not used outside of clk-cpu-8996.c, so this commit marks it static. Fixes: 03e342dc ("clk: qcom: Add CPU clock driver for msm8996") Reported-by:
Hulk Robot <hulkci@huawei.com> Signed-off-by:
Wei Yongjun <weiyongjun1@huawei.com> Link: https://lore.kernel.org/r/20200714142155.35085-1-weiyongjun1@huawei.comSigned-off-by:
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Sivaprakash Murugesan authored
The PCIe clocks GCC_PCIE0_AXI_S_BRIDGE_CLK, GCC_PCIE0_RCHNG_CLK_SRC, GCC_PCIE0_RCHNG_CLK are wrongly added to the gcc reset group. Move them to the gcc clock group. Reported-by:
kernel test robot <lkp@intel.com> Signed-off-by:
Sivaprakash Murugesan <sivaprak@codeaurora.org> Link: https://lore.kernel.org/r/1594877570-9280-1-git-send-email-sivaprak@codeaurora.org Fixes: e7fb524c ("dt-bindings: clock: qcom: ipq8074: Add missing bindings for PCIe") Signed-off-by:
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- 11 Jul, 2020 6 commits
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Konrad Dybcio authored
Add rpm smd clocks, PMIC and bus clocks which are required on MSM8992, MSM8994 (and APQ variants) for clients to vote on. Signed-off-by:
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Sivaprakash Murugesan authored
Add missing clocks and resets for pcie port0 of ipq8074 devices. Co-developed-by:
Selvam Sathappan Periakaruppan <speriaka@codeaurora.org> Signed-off-by:
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Sivaprakash Murugesan authored
Add missing clock bindings for PCIe port0 of ipq8074. Co-developed-by:
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Loic Poulain authored
Each of the CPU clusters (Power and Perf) on msm8996 are clocked via 2 PLLs, a primary and alternate. There are also 2 Mux'es, a primary and secondary all connected together as shown below +-------+ XO | | +------------------>0 | | | PLL/2 | SMUX +----+ +------->1 | | | | | | | +-------+ | +-------+ | +---->0 | | | | +---------------+ | +----------->1 | CPU clk |Primary PLL +----+ PLL_EARLY | | +------> | +------+-----------+ +------>2 PMUX | +---------------+ | | | | | +------+ | +-->3 | +--^+ ACD +-----+ | +-------+ +---------------+ +------+ | |Alt PLL | | | +---------------------------+ +---------------+ PLL_EARLY The primary PLL is what drives the CPU clk, except for times when we are reprogramming the PLL itself (for rate changes) when we temporarily switch to an alternate PLL. A subsequent patch adds support to switch between primary and alternate PLL during rate changes. The primary PLL operates on a single VCO range, between 600MHz and 3GHz. However the CPUs do support OPPs with frequencies between 300MHz and 600MHz. In order to support running the CPUs at those frequencies we end up having to lock the PLL at twice the rate and drive the CPU clk via the PLL/2 output and SMUX. So for frequencies above 600MHz we follow the following path Primary PLL --> PLL_EARLY --> PMUX(1) --> CPU clk and for frequencies between 300MHz and 600MHz we follow Primary PLL --> PLL/2 --> SMUX(1) --> PMUX(0) --> CPU clk ACD stands for Adaptive Clock Distribution and is used to detect voltage droops. Signed-off-by:Rajendra Nayak <rnayak@codeaurora.org> Rajendra Nayak: Initial RFC - https://lkml.org/lkml/2016/9/29/84Signed-off-by:
Ilia Lin <ilialin@codeaurora.org> Ilia Lin: - reworked clock registering - Added clock-tree diagram - non-builtin support - clock notifier on rate change - https://lkml.org/lkml/2018/5/24/123Signed-off-by:
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Ilia Lin authored
Each of the CPU clusters (Power and Perf) on msm8996 are clocked via 2 PLLs, a primary and alternate. There are also 2 Mux'es, a primary and secondary all connected together as shown below +-------+ XO | | +------------------>0 | | | PLL/2 | SMUX +----+ +------->1 | | | | | | | +-------+ | +-------+ | +---->0 | | | | +---------------+ | +----------->1 | CPU clk |Primary PLL +----+ PLL_EARLY | | +------> | +------+-----------+ +------>2 PMUX | +---------------+ | | | | | +------+ | +-->3 | +--^+ ACD +-----+ | +-------+ +---------------+ +------+ | |Alt PLL | | | +---------------------------+ +---------------+ PLL_EARLY The primary PLL is what drives the CPU clk, except for times when we are reprogramming the PLL itself (for rate changes) when we temporarily switch to an alternate PLL. A subsequent patch adds support to switch between primary and alternate PLL during rate changes. The primary PLL operates on a single VCO range, between 600MHz and 3GHz. However the CPUs do support OPPs with frequencies between 300MHz and 600MHz. In order to support running the CPUs at those frequencies we end up having to lock the PLL at twice the rate and drive the CPU clk via the PLL/2 output and SMUX. Signed-off-by: -
Ilia Lin authored
The driver provides kernel level API for other drivers to access the MSM8996 L2 cache registers. Separating the L2 access code from the PMU driver and making it public to allow other drivers use it. The accesses must be separated with a single spinlock, maintained in this driver. Signed-off-by:
Will Deacon <will@kernel.org> Signed-off-by:
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- 29 Jun, 2020 1 commit
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Wei Yongjun authored
In case of error, the function dev_get_regmap() returns NULL pointer not ERR_PTR(). The IS_ERR() test in the return value check should be replaced with NULL test. Fixes: 5e77b4ef ("clk: qcom: Add ipq6018 apss clock controller") Reported-by:
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- 23 Jun, 2020 2 commits
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Vincent Knecht authored
Add missing definition of rpm clk for msm8936 soc (also used by msm8939) Signed-off-by:
Vincent Knecht <vincent.knecht@mailoo.org> Link: https://lore.kernel.org/r/20200613072745.1249003-2-vincent.knecht@mailoo.orgSigned-off-by:
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Vincent Knecht authored
Acked-by:
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- 22 Jun, 2020 5 commits
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Konrad Dybcio authored
Add rpm smd clocks, PMIC and bus clocks which are required on SDM630/660 (and APQ variants) for clients to vote on. Signed-off-by:
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Sivaprakash Murugesan authored
The CPU on Qualcomm ipq6018 devices are clocked primarily by a aplha PLL and xo which are connected to a mux and enable block. Add support for the mux and enable block which feeds the CPU on ipq6018 devices. Reviewed-by:
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Sivaprakash Murugesan authored
Add dt-binding for ipq6018 apss clock controller Acked-by:
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Sivaprakash Murugesan authored
The CPUs on Qualcomm ipq based devices are clocked by an alpha PLL. Add support for the apss pll found on ipq based devices which can support CPU frequencies above 1Ghz. Signed-off-by:
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Sivaprakash Murugesan authored
cpus on ipq6018 are clocked by a53 pll, add device compatible for a53 pll found on ipq6018 devices. Reviewed-by:
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- 14 Jun, 2020 3 commits
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Linus Torvalds authored
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git://github.com/micah-morton/linuxLinus Torvalds authored
Pull SafeSetID update from Micah Morton: "Add additional LSM hooks for SafeSetID SafeSetID is capable of making allow/deny decisions for set*uid calls on a system, and we want to add similar functionality for set*gid calls. The work to do that is not yet complete, so probably won't make it in for v5.8, but we are looking to get this simple patch in for v5.8 since we have it ready. We are planning on the rest of the work for extending the SafeSetID LSM being merged during the v5.9 merge window" * tag 'LSM-add-setgid-hook-5.8-author-fix' of git://github.com/micah-morton/linux: security: Add LSM hooks to set*gid syscalls
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Thomas Cedeno authored
The SafeSetID LSM uses the security_task_fix_setuid hook to filter set*uid() syscalls according to its configured security policy. In preparation for adding analagous support in the LSM for set*gid() syscalls, we add the requisite hook here. Tested by putting print statements in the security_task_fix_setgid hook and seeing them get hit during kernel boot. Signed-off-by:
Thomas Cedeno <thomascedeno@google.com> Signed-off-by:
Micah Morton <mortonm@chromium.org>
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