- 23 Aug, 2017 1 commit
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git://github.com/baylibre/clk-mesonStephen Boyd authored
Pull Amlogic clock driver updates from Neil Armstrong: * meson8b: add the reset controller to the clkc * meson: expose all clk ids * gxbb-aoclk: Add CEC 32k clock * gxbb: add mmc input 0 clocks * meson: fix protection against undefined clks * gxbb: fix audio divider flags * tag 'meson-clk-for-4.14' of git://github.com/baylibre/clk-meson: clk: meson: gxbb-aoclk: Add CEC 32k clock clk: meson: gxbb-aoclk: Switch to regmap for register access dt-bindings: clock: amlogic, gxbb-aoclkc: Update bindings clk: meson: gxbb: Add sd_emmc clk0 clocks clk: meson: gxbb: fix clk_mclk_i958 divider flags clk: meson: gxbb: fix meson cts_amclk divider flags clk: meson: meson8b: register the built-in reset controller dt-bindings: clock: gxbb-aoclk: Add CEC 32k clock clk: meson: gxbb: Add sd_emmc clk0 clkids clk: meson-gxbb: expose almost every clock in the bindings clk: meson8b: expose every clock in the bindings clk: meson: gxbb: fix protection against undefined clks clk: meson: meson8b: fix protection against undefined clks dt-bindings: clock: meson8b: describe the embedded reset controller
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- 04 Aug, 2017 13 commits
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Neil Armstrong authored
The CEC 32K AO Clock is a dual divider with dual counter to provide a more precise 32768Hz clock for the CEC subsystem from the external xtal. Signed-off-by:Neil Armstrong <narmstrong@baylibre.com>
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Neil Armstrong authored
Switch the aoclk driver to use the new bindings and switch all the registers access to regmap only. Signed-off-by: -
Neil Armstrong authored
On the first revision of the bindings, only the gates + resets were known in the AO Clock HW, but more registers used to configures AO clock are known to be spread among the AO register space. This patch adds a parent node for the entire system control zone for the AO domain then moves the clock controller as a subnode of the system control node. Signed-off-by: -
Jerome Brunet authored
Input source 0 of the mmc controllers is not directly xtal, as currently described in DT. Each controller is fed by a composite clock (the usual mux, divider and gate). The muxes inputs are the xtal (default) and the fclk_div clocks. These parents, along with the divider, should be able to provide the necessary rates for mmc and nand operation. The input muxes should also be able to take mpll2, mpll3 and gp0_pll but these are precious clocks, needed for other usage. It is better if the mmc does not use these them. For this reason, mpll2, mpll3 and gp0_pll is not listed among the possible parents. Signed-off-by:
Jerome Brunet <jbrunet@baylibre.com> Signed-off-by:
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Jerome Brunet authored
CLK_DIVIDER_ROUND_CLOSEST was incorrectly put in the hw.init flags while it should have been in the divider flags Fixes: 3c277c24 ("clk: meson: gxbb: add cts_mclk_i958") Signed-off-by:
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Jerome Brunet authored
CLK_DIVIDER_ROUND_CLOSEST was incorrectly put in the hw.init flags while it should have been in the divider flags Fixes: 4087bd4b ("clk: meson: gxbb: add cts_amclk") Signed-off-by:
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Martin Blumenstingl authored
The clock controller also includes some reset lines. This patch implements a reset controller to assert and de-assert these resets. The reset controller itself is registered early (through CLK_OF_DECLARE_DRIVER) because it is needed very early in the boot process (to start the secondary CPU cores). According to the public S805 datasheet there are two more reset bits in the HHI_SYS_CPU_CLK_CNTL0 register, which are not implemented by this patch (as these seem to be unused in Amlogic's vendor Linux kernel sources and their u-boot tree): - bit 15: GEN_DIV_SOFT_RESET - bit 14: SOFT_RESET All information was taken from the public S805 Datasheet and Amlogic's vendor GPL kernel sources. This patch is based on an earlier version submitted by Carlo Caione. Suggested-by:
Carlo Caione <carlo@endlessm.com> Signed-off-by:
Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by:
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Neil Armstrong authored
This patchadds the clock binding entry for the CEC 32K AO Clock. Signed-off-by: -
Jerome Brunet authored
Add the clkids for the clocks feeding the input0 of the mmc controllers Signed-off-by:
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Jerome Brunet authored
Expose all clocks which maybe used as DT bindings Only clock ids internal the controller remain un-exposed Acked-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
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Jerome Brunet authored
Expose all clocks which maybe used as DT bindings Only clock ids internal the controller remain un-exposed (none on this particular controller at the moment) Acked-by:
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Jerome Brunet authored
gxbb clock driver gracefully handles case where the clkid is defined but the clock hw pointer is not provided, as long as it is not at the end of the hw_onecell_data array. This patch ensure that the last entries are defined as well to handle this particular case. Fixes: a70c6e06 ("clk: meson: gxbb: protect against holes in the onecell_data array") Signed-off-by:
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Jerome Brunet authored
meson8b clock driver gracefully handles case where the clkid is defined but the clock hw pointer is not provided, as long as it is not at the end of the hw_onecell_data array. This patch ensure that the last entries are defined as well to handle this particular case. Fixes: e92f7cca ("clk: meson8b: clean up fixed rate clocks") Signed-off-by:
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- 03 Aug, 2017 3 commits
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Masahiro Yamada authored
This SoC is too old. It is difficult to maintain any longer. Signed-off-by:
Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Stephen Boyd <sboyd@codeaurora.org>
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Stephen Boyd authored
* clk-fixes: clk: keystone: sci-clk: Fix sci_clk_get clk: meson: mpll: fix mpll0 fractional part ignored clk: samsung: exynos5420: The EPLL rate table corrections clk: sunxi-ng: sun5i: Add clk_set_rate_parent to the CPU clock
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Tero Kristo authored
Currently a bug in the sci_clk_get implementation causes it to always return a clock belonging to the last device in the static list of clock data. This is due to a bug in the init code that causes the array used by sci_clk_get to only be populated with the clocks for the last device, as each device overwrites the entire array with its own clocks. Fix this by calculating the actual number of clocks for the SoC, and allocating the whole array in one go. Also, we don't need the handle to the init data array anymore after doing this, instead we can just compare the dev_id / clk_id against the registered clocks and use binary search for speed. Signed-off-by:
Tero Kristo <t-kristo@ti.com> Reported-by:
Dave Gerlach <d-gerlach@ti.com> Fixes: b745c079 ("clk: keystone: Add sci-clk driver support") Cc: Nishanth Menon <nm@ti.com> Tested-by:
Franklin Cooper <fcooper@ti.com> Signed-off-by:
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- 02 Aug, 2017 2 commits
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Stephen Boyd authored
Merge tag 'sunxi-clk-fixes-for-4.13' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-fixes Pull one Allwinner clock fix from Chen-Yu Tsai: One critical clock fix for sun5i (A10s/A13/R8) which enables propagation of clock rate changes from the "cpu" clock to it's parent PLL clock. This fixes cpufreq related crashes that have been observed on KernelCI with the C.H.I.P. and multi_v7_defconfig. * tag 'sunxi-clk-fixes-for-4.13' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi-ng: sun5i: Add clk_set_rate_parent to the CPU clock
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git://github.com/baylibre/clk-mesonStephen Boyd authored
Pull one Meson clock fix from Neil Armstrong * tag 'meson-clk-fixes-for-4.13-rc4-v2' of git://github.com/baylibre/clk-meson: clk: meson: mpll: fix mpll0 fractional part ignored
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- 01 Aug, 2017 1 commit
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Jerome Brunet authored
mpll0 clock is special compared to the other mplls. It needs another bit (ssen) to be set to activate the fractional part the mpll divider Fixes: 007e6e5c ("clk: meson: mpll: add rw operation") Signed-off-by:
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- 31 Jul, 2017 2 commits
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Sylwester Nawrocki authored
This patch fixes values of the EPLL K coefficient and changes the EPLL output frequency values to match exactly what is possible to achieve with given M, P, S, K coefficients. This allows to avoid rounding errors and unexpected frequency being set with clk_set_rate(), due to recalc_rate returning different values than the PLL rate specified in the exynos5420_epll_24mhz_tbl table. E.g. this prevents a case where two consecutive clk_set_rate() calls with same argument result in different PLL output frequency. The PLL output frequencies have been calculated with formula: f = fxtal * (M * 2^16 + K) / (P * 2^S) / 2^16 where fxtal = 24000000. Fixes: 9842452a ("clk: samsung: exynos542x: Add EPLL rate table") Signed-off-by:
Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by:
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Martin Blumenstingl authored
The Amlogic Meson8/Meson8b/Meson8m2 clock controller provides some reset lines. These are used for example to boot the secondary CPU cores. This patch describes the reset controller which is embedded into the clock controller on these SoCs. A header file is provided which provides preprocessor macros for each reset line (to make the .dts files easier to read). Signed-off-by:
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- 24 Jul, 2017 1 commit
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Maxime Ripard authored
The current CPU clock is missing the option to change the rate of its parents, leading to improper rates calculated by cpufreq, and eventually crashes. Cc: <stable@vger.kernel.org> Fixes: 5e737617 ("clk: sunxi-ng: Add sun5i CCU driver") Reported-by:
Kevin Hilman <khilman@baylibre.com> Acked-by:
Chen-Yu Tsai <wens@csie.org> Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com>
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- 21 Jul, 2017 3 commits
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Rob Herring authored
Now that we have a custom printf format specifier, convert users of full_name to use %pOF instead. This is preparation to remove storing of the full path string for each node. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Acked-by:
James Liao <jamesjj.liao@mediatek.com> Acked-by:
Alexandre TORGUE <alexandre.torgue@st.com> Reviewed-by:
Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by:
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Yuantian Tang authored
Register each PLL and its division clocks to clock lookup table to facilitate the clock look up for clock consumer. Signed-off-by:
Tang Yuantian <andy.tang@nxp.com> Signed-off-by:
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Yuantian Tang authored
Clock on ls1088a chip takes primary clocking input from the external SYSCLK signal. The SYSCLK input (frequency) is multiplied using multiple phase locked loops (PLL) to create a variety of frequencies which can then be passed to a variety of internal logic, including cores and peripheral IP modules. Signed-off-by:
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- 18 Jul, 2017 6 commits
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Stephen Boyd authored
* clk-fixes: clk: x86: Do not gate clocks enabled by the firmware clk: gemini: Fix reset regression
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Carlo Caione authored
Read the enable register to determine if the clock is already in use by the firmware. In this case avoid gating the clock. Tested-by:
Enric Balletbo i Serra <enric.balletbo@collabora.com> Acked-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by:
Darren Hart (VMware) <dvhart@infradead.org> Signed-off-by:
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Julia Lawall authored
Drop static on a local variable, when the variable is initialized before any possible use. Thus, the static has no benefit. The semantic patch that fixes this problem is as follows: (http://coccinelle.lip6.fr/) // <smpl> @bad exists@ position p; identifier x; type T; @@ static T x@p; ... x = <+...x...+> @@ identifier x; expression e; type T; position p != bad.p; @@ -static T x@p; ... when != x when strict ?x = e; // </smpl> Signed-off-by:
Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by:
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Gustavo A. R. Silva authored
Remove unnecessary static on local variable _base_ in both functions moxart_of_pll_clk_init() and moxart_of_apb_clk_init(). Such variables are initialized before being used, on every execution path throughout the mentioned functions. The statics have no benefit and, removing them reduce the code size. This issue was detected using Coccinelle and the following semantic patch: @bad exists@ position p; identifier x; type T; @@ static T x@p; ... x = <+...x...+> @@ identifier x; expression e; type T; position p != bad.p; @@ -static T x@p; ... when != x when strict ?x = e; In the following log you can see the difference in the code size. Also, notice that the bss segment is reduced down to zero. This log is the output of the size command, before and after the code change: before: text data bss dec hex filename 1724 384 128 2236 8bc drivers/clk/clk-moxart.o after: text data bss dec hex filename 1697 240 0 1937 791 drivers/clk/clk-moxart.o Signed-off-by:Gustavo A. R. Silva <garsilva@embeddedor.com> Signed-off-by:
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Georgi Djakov authored
As there is no way to actually query the hardware for the current clock rate, now racalc_rate() just returns the last rate that was previously set. But if the rate was not set yet, we return the bogus rate of 1000Hz. The branch clocks have the same rate as their parent, so in this case we just need to remove recalc_rate ops and then the core framework will handle this automagically. The round_rate() is unused, so remove it as well. Reported-by:
Archit Taneja <architt@codeaurora.org> Fixes: 00f64b58 ("clk: qcom: Add support for SMD-RPM Clocks") Signed-off-by:
Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by:
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Sean Wang authored
Fixed the signedness bug returning '(-22)' on the return type as u8 with removing the sanity checker in clk_cpumux_get_parent() since clk_cpumux_set_parent() always ensures validity in clk_cpumux_get_parent() got called. Fixes: 1e17de90 ("clk: mediatek: add missing cpu mux causing Mediatek cpufreq can't work") Reported-by:
Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
Sean Wang <sean.wang@mediatek.com> Signed-off-by:
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- 17 Jul, 2017 8 commits
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Linus Walleij authored
commit e2860e1f ("serial: 8250_of: Add reset support") introduced reset support for the 8250_of driver. However it unconditionally uses the assert/deassert pair to deassert reset on the device at probe and assert it at remove. This does not work with systems that have a self-deasserting reset controller, such as Gemini, that recently added a reset controller. As a result, the console will not probe on the Gemini with this message: Serial: 8250/16550 driver, 1 ports, IRQ sharing disabled of_serial: probe of 42000000.serial failed with error -524 This (-ENOTSUPP) is the error code returned by the deassert() operation on self-deasserting reset controllers. To work around this, implement dummy .assert() and .deassert() operations in the Gemini combined clock and reset controller. This fixes the issue on this system. Cc: Joel Stanley <joel@jms.id.au> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: linux-serial@vger.kernel.org Fixes: e2860e1f ("serial: 8250_of: Add reset support") Signed-off-by:
Linus Walleij <linus.walleij@linaro.org> Acked-by:
Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by:
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Vladimir Barinov authored
IDT VersaClock 5 5P49V5925 has 5 clock outputs, 4 fractional dividers. Input clock source can be taken only from external reference clock. Signed-off-by:
Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com> Acked-by:
Marek Vasut <marek.vasut@gmail.com> Signed-off-by:
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Vladimir Barinov authored
Update IDT VersaClock 5 driver to support 5P49V5925. This chip has only external clock input, four fractional dividers (FODs) and five clock outputs (four universal clock outputs and one reference clock output at OUT0_SELB_I2C). Signed-off-by:
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Marek Vasut authored
Update IDT VersaClock 5 driver to support IDT VersaClock 6 5P49V6901. This chip has two clock inputs (external XTAL or external CLKIN), four fractional dividers (FODs) and five clock outputs (four universal clock outputs and one reference clock output at OUT0_SELB_I2C). Signed-off-by:
Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Alexey Firago <alexey_firago@mentor.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Cc: linux-renesas-soc@vger.kernel.org Tested-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> on Salvator-XS with the display LVDS output. Signed-off-by:
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Marek Vasut authored
IDT VersaClock 6 5P49V6901 has 4 clock outputs, 4 fractional dividers. Input clock source can be taken from either external crystal or from external reference clock. Signed-off-by:
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Marek Vasut authored
The VersaClock 6 has an input frequency doubler between the input clock mux and the predivider. Add new capability flag and support for this frequency doubler block into the driver. Signed-off-by:
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Marek Vasut authored
Split the VC5 clock input mux and the predivider to more accurately model the hardware and fix the previously incorrect assumption that both the OUT_SEL_I2CB and the PLL are fed from the predivider. It is in fact the clock input mux output which is directly feeding the clock into the OUT_SEL_I2CB output, while the clock input mux output first passes through the predivider before it is fed into the PLL. Signed-off-by:
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Marek Vasut authored
The output buffer input mux can be configured in either of three states -- disabled, input from FOD, input from previous output. Once the .prepare() callback of the output buffer is called, the output buffer input mux must be set to either input from FOD or input from previous output, it cannot be set to Disabled anymore or the output won't work. Default to the input from FOD if the output buffer input mux was Disabled and the .prepare() was called on it. Note that we do not set the output buffer input mux back to Disabled in the .unprepare() callback as there is no obvious benefit of doing so. We disable the entire output buffer in the .unprepare() callback already. Signed-off-by:
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