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- 09 Jun, 2023 31 commits
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Felix Kuehling authored
On GFXv9.4.3 NUMA APUs, system memory locality must be determined per page to choose the correct MTYPE. This patch adds a GMC callback that can provide this per-page override and implements it for native mode. Carve-out mode is not yet supported and will use the safe default (remote) MTYPE for system memory. Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-and-tested-by:
Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Felix Kuehling authored
Treat system memory on NUMA systems as remote by default. Overriding with a more efficient MTYPE per page will be implemented in the next patch. No need for a special case for APP APUs. System memory is handled the same for carve-out and native mode. And VRAM doesn't exist in native mode. Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-and-tested-by:
Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Graham Sider authored
By default, set use_mtype_cc_wa to 1 to set PTE coherence flag MTYPE_CC instead of MTYPE_RW by default. This is required for the time being to mitigate a bug causing XCCs to hit stale data due to TCC marking fully dirty lines as exclusive. Signed-off-by:
Graham Sider <Graham.Sider@amd.com> Reviewed-by:
Joseph Greathouse <Joseph.Greathouse@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Graham Sider authored
Invalidate TLBs via a legacy flush request (flush_type=0) prior to the heavyweight flush requests (flush_type=2) in gmc_v9_0.c. This is temporarily required to mitigate a bug causing CPC UTCL1 to return stale translations after invalidation requests in address range mode. v2: squash in long term fix "drm/amdgpu: disable extra gfx943 legacy flush on rev1+" Signed-off-by:
Graham Sider <Graham.Sider@amd.com> Reviewed-by:
Philip Yang <Philip.Yang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Gavin Wan authored
For SRIOV, the memory partitions are set on host drover. Each VF only has one memory partition. We need set the memory partitions to 1 on guest driver for SRIOV. V2: sqaush in fix ("drm/amdgpu: Fix memory range info of GC 9.4.3 VFs") Signed-off-by:
Gavin Wan <Gavin.Wan@amd.com> Acked-by:
Zhigang Luo <zhigang.luo@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Gavin Wan authored
The MC_VM_FB_OFFSET is PF only register. It cannot be read on VF. So, the driver should not use MC_VM_FB_OFFSET address to set the address of dev->gmc.aper_base. Signed-off-by:
Gavin Wan <Gavin.Wan@amd.com> Reviewed-by:
Zhigang Luo <zhigang.luo@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Lijo Lazar authored
GC 9.4.3 ASICS may have memory split into multiple partitions.Initialize the memory partition information for each range. The information may be in the form of a numa node id or a range of pages. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Le Ma <le.ma@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Lijo Lazar authored
Expand the interface to get supported memory partition modes also along with the current memory partition mode. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Le Ma <le.ma@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Lijo Lazar authored
GMC block handles memory related information, it makes more sense to keep memory partition functions in gmc block. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Le Ma <le.ma@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Rajneesh Bhardwaj authored
[For 1P NPS1 mode driver bringup] Changes required to initialize the amdgpu driver with frontdoor firmware loading and discovery=2 with the native mode SBIOS that enables CPU GPU unified interleaved memory. sudo modprobe amdgpu discovery=2 Once PSP TMR region is reported via the ACPI interface, the dependency on the ip_discovery.bin will be removed. Choice of where to allocate driver table is given to each IP version. In general, both GTT and VRAM domains will be considered. If one of the tables has a strict restriction for VRAM domain, then only VRAM domain is considered. Reviewed-by:
Felix Kuehling <felix.kuehling@amd.com> (lijo: Modified the handling for SMU Tables) Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Hawking Zhang authored
Initialize mmhub v1_8 ras function. Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Graham Sider authored
Revert temporary dGPU VRAM MTYPE setting and align with expected coherency protocol. Signed-off-by:
Graham Sider <Graham.Sider@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Felix Kuehling authored
Some AMD APUs may not have a dedicated VRAM. On such platforms the GART table should be allocated on the system memory. When real vram size is zero, place the GART table in system memory and create an SG BO to make it GPU accessible. v2: fix includes Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> (rajneesh: removed set_memory_wc workaround) Signed-off-by:
Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> Signed-off-by:
Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Lijo Lazar authored
ASICs with GFX 9.4.3 support 48-bit addressing. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Lijo Lazar authored
Use the right register for semaphore release during invalidation. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Le Ma <le.ma@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Le Ma authored
The AMDGPU_GFXHUB was bind to each xcc in the logical order. Thus convert the node_id to logical xcc_id to index the correct AMDGPU_GFXHUB. And "node_id / 4" can get the correct AMDGPU_MMHUB0 index. Signed-off-by:
Le Ma <le.ma@amd.com> Tested-by:
Asad kamal <asad.kamal@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Rajneesh Bhardwaj authored
Apply the GFXIP 9.4.3 specific snoop and mtype settings for various scenarios such as APU, APU in Carveout mode and dGPU mode. Note: This is expected to change due to: 1 - NPS > 1 support in future 2 - Hardware bugs found during initial asic bringup. Cc: Graham Sider <graham.sider@amd.com> Cc: Hawking Zhang <hawking.zhang@amd.com> Signed-off-by:
Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Lijo Lazar authored
Use a mask of available active clusters instead of using only the number of active clusters. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Rajneesh Bhardwaj authored
On GPXIP 9.4.3 APU, in no carveout mode there is no real vram heap and could be emulated by the driver over the interleaved NUMA system memory and the APU could also be in the carveout mode during early development stage or otherwise for debugging purpose so introduce a new member in amdgpu_gmc to figure out whether the APU is in the native mode as per the production configuration. AMD_IS_APU cannot be used for Accelerated Processing Platform APUs as it might be used in a different context on previous generations or on small APUs. Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Tested-by:
Graham Sider <graham.sider@amd.com> Signed-off-by:
Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Philip Yang authored
Output IH cookie node_id and translate it to the corresponding AID id and XCC id, to help debug the GPU page fault. Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Mukul Joshi authored
Update interrupt handling in CPX mode for GFX9.4.3 by using the VMID space instead of SDMA client id to determine if an interrupt should be processed by a KFD node. This is especially needed for handling retry faults from MMHUB. Signed-off-by:
Mukul Joshi <mukul.joshi@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Sierra authored
This work is required for GC 9.4.3, previous to support memory partitions per node at SVM. When multiple partition is configured, every BO should be allocated inside one specific partition which corresponds to the current amdgpu_device and kfd_node. v2: squash in compilation fix (Alex) v3: squash in fix for pre-gfx 9.4.3 (Alex) v4: squash in best_loc fix (Alex) Signed-off-by:
Alex Sierra <alex.sierra@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Lijo Lazar authored
Instead of number of XCCs, keep a mask of XCCs for the exact XCCs available on the ASIC. XCC configuration could differ based on different ASIC configs. v2: Rename num_xcd to num_xcc (Hawking) Use smaller xcc_mask size, changed to u16 (Le) Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Le Ma <Le.Ma@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Shiwu Zhang authored
Add the xgmi LFB_CNTL/LBF_SIZE reg addresses to fetch the xgmi info from. v2: move get_xgmi_info() to GC_V9_4_3 sepecific source files to utilize the register definitions specific for GC_V9_4_3 v3: remove the duplicated register definitions v4: enable xgmi based on asic_type as XGMI_IP ver is not available yet for IP discovery Signed-off-by:
Shiwu Zhang <shiwu.zhang@amd.com> Reviewed-by:
Le Ma <Le.Ma@amd.com> Ack-by:
Lijo Lazar <Lijo.Lazar@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Le Ma authored
Like GFXHUB, set MMHUB0 bitmask for each AID. Signed-off-by:
Le Ma <le.ma@amd.com> Acked-by:
Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Mukul Joshi authored
Fix VM fault reporting and clear VM fault register for XCC1. Signed-off-by:
Mukul Joshi <mukul.joshi@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Mukul Joshi authored
Add XCC instance to select the correct KIQ ring when flushing TLBs on a multi-XCC setup. Signed-off-by:
Mukul Joshi <mukul.joshi@amd.com> Tested-by:
Amber Lin <Amber.Lin@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Le Ma authored
Each XCD owns one GFXHUB. v2: switch to the new VMHUB layout Signed-off-by:
Le Ma <le.ma@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Le Ma authored
As the layout of VMHUB definition has been changed to cover multiple XCD/AID case, the original num_vmhubs is not appropriate to do vmhub iteration any more. Drop num_vmhubs and introduce vmhubs_mask instead. v2: switch to the new VMHUB layout v3: use DECLARE_BITMAP to define vmhubs_mask Signed-off-by:
Le Ma <le.ma@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Hawking Zhang authored
v1: Each partition has its own gfxhub or mmhub. adjust the num of MAX_VMHUBS and the GFXHUB/MMHUB layout (Le) v2: re-design the AMDGPU_GFXHUB/AMDGPU_MMHUB layout (Le) v3: apply the gfxhub/mmhub layout to new IPs (Hawking) v4: fix up gmc11 (Alex) v5: rebase (Alex) Signed-off-by:
Le Ma <le.ma@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Hamza Mahfooz authored
As made mention of in commit c56edea58c31 ("drm/amdgpu: fix amdgpu_irq_put call trace in gmc_v10_0_hw_fini") and commit aa6ac247ed7d ("drm/amdgpu: fix amdgpu_irq_put call trace in gmc_v11_0_hw_fini"). It is meaningless to call amdgpu_irq_put() for gmc.ecc_irq. So, remove it from gmc_v9_0_hw_fini(). Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2522 Fixes: c8b5a95b ("drm/amdgpu: Fix desktop freezed after gpu-reset") Reviewed-by:
Mario Limonciello <mario.limonciello@amd.com> Signed-off-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- 18 Apr, 2023 1 commit
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Le Ma authored
v1: more kiq instances are a available in SOC (Le) v2: squash commits to avoid breaking the build (Le) v3: make the conversion for gfx/mec v11_0 (Hawking) Signed-off-by:
Le Ma <le.ma@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- 14 Apr, 2023 1 commit
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Le Ma authored
It looks better to place this field in ring structure. Also drop the repeated ring funcs definitions if there's no difference except for vmhub field. v2: rename the field to vm_hub like others (Le) v3: apply the changes to new ip blocks (Hawking) v4: fix vcn sw ring (Alex) Signed-off-by:
Le Ma <le.ma@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- 13 Apr, 2023 1 commit
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Mukul Joshi authored
This patch enables the IH retry CAM on GFX9 series cards. This retry filter is used to prevent sending lots of retry interrupts in a short span of time and overflowing the IH ring buffer. This will also help reduce CPU interrupt workload. Signed-off-by:
Mukul Joshi <mukul.joshi@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- 31 Mar, 2023 2 commits
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Le Ma authored
Initialize gfxhub1.2 and mmhub1.8 function calls Signed-off-by:
Le Ma <le.ma@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Hawking Zhang authored
Initialize various gmc sw/hw settings/configurations for GC 9.4.3. Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Le Ma <Le.Ma@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- 15 Mar, 2023 2 commits
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Hawking Zhang authored
To align with other IP blocks. Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Stanley Yang <Stanley.Yang@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Hawking Zhang authored
To align with other IP blocks Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Stanley Yang <Stanley.Yang@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- 13 Mar, 2023 2 commits
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Hawking Zhang authored
Initialize hdp ras block only when mmhub ip block supports ras features. Driver queries ras capabilities after early_init, ras block init needs to be moved to sw_init. Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Stanley Yang <Stanley.Yang@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Hawking Zhang authored
Initialize mmhub ras block only when mmhub ip block supports ras features. Driver queries ras capabilities after early_init, ras block init needs to be moved to sw_init. Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Stanley Yang <Stanley.Yang@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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