- 26 Oct, 2020 25 commits
-
-
Aric Cyr authored
[Why] When ODM combine is in use we trigger multiple update events causing issues with variable refresh rate. [How] Only trigger on a single ODM instance. Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
-
Alvin Lee authored
[Why] We should leave GSL if we're not doing immediate flip no matter if we're doing pipe split or not [How] Check for updating GSL state whenever we're not doing immediate flip v2: Squash in build fix (Alex) Signed-off-by:
Alvin Lee <alvin.lee2@amd.com> Acked-by:
-
Yu-Ting Shen authored
[WHY] VBIOS will not enable VSC_SDP during pre-OS to lead MISC1[6] wasn't matched with driver. [HOW] disabled seamless boot if sink supports VSC_SDP Signed-off-by:
Yu-Ting Shen <Yu-ting.Shen@amd.com> Acked-by:
-
Yongqiang Sun authored
[Why] right side visual confirm is too thick due to it is 4 times of left side (16 lines). [How] Change factor from 4 to 2. Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Acked-by:
-
Isabel Zhang authored
[Why] Causes underflow regression [How] This reverts commit 99d1437aSigned-off-by:
Isabel Zhang <isabel.zhang@amd.com> Acked-by:
-
Brandon Syu authored
[Why] For some monitors, they can't display under BIOS with avmute enabled. [How] Add monitor patch for skip avmute action. Signed-off-by:
Brandon Syu <Brandon.Syu@amd.com> Acked-by:
-
Roman Li authored
[Why] All DCN3x resources share ABM_MASK_SH_LIST_DCN301 definition. The naming is misleading since it looks like DCN30 code depends on next version DCN301, which in fact is vice-versa. [How] Refactor the naming to ABM_MASK_SH_LIST_DCN30. v2: squash in build fixes (Alex) Signed-off-by:
Roman Li <roman.li@amd.com> Acked-by:
-
Martin Leung authored
why: missing OEM data to control graphics card functions how: load it into init_data. copied over from dcn2 implementation. copied destruction sequence as well. Signed-off-by:
Martin Leung <martin.leung@amd.com> Acked-by:
-
Sung Lee authored
[WHY & HOW] Currently disable 48mhz debug option only disables on boot. Need to put option check in update_clocks as well to make it affect more areas. Signed-off-by:
Sung Lee <sung.lee@amd.com> Acked-by:
-
Aric Cyr authored
Signed-off-by:
-
Nikola Cornij authored
[Why] Can be used for debug purposes [How] Add max target bpp override field and related handling Signed-off-by:
Nikola Cornij <nikola.cornij@amd.com> Acked-by:
-
Anthony Koo authored
| [Header Changes] | - Add GPINT to change timestamping mode for traces Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
-
Reza Amini authored
[why] So we can track VSC SDP errors from display [how] Define the bit, and use it in driver logic Signed-off-by:
Reza Amini <Reza.Amini@amd.com> Acked-by:
-
Taimur Hassan authored
[Why] Underflow counter increases in AGM when performing some mode switches due to timing sync, which is a known hardware issue. [How] Temporarily raise DPG height during timing sync so that underflow is not reported. Signed-off-by:
Taimur Hassan <syed.hassan@amd.com> Acked-by:
-
Alvin Lee authored
[Why] If full pstate is not supported, we should set WM set A to 0 to prevent any hangs [How] If pstate is not supported, set watermark set A to 0 Signed-off-by:
-
Eryk Brol authored
This reverts commit c44a22b3. Reason for revert: Patch introduces performance issues and might cause memory consistency problems with multiple connectors. Signed-off-by:
Eryk Brol <eryk.brol@amd.com> Acked-by:
-
Ashley Thomas authored
[Why] Some sink devices wish to have access to the minimum HBlank supported by the ASIC. [How] Make the ASIC minimum HBlank available in Source Device information address 0x340. Signed-off-by:
Ashley Thomas <Ashley.Thomas2@amd.com> Acked-by:
-
Dmytro Laktyushkin authored
[WHY & HOW] Enable ODM Combine + Fullscreen MPO on DCN2.1 For lower power consumption in video use cases. Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Signed-off-by:
-
Dmytro Laktyushkin authored
[Why&How] Create a separate dcn21_fast_validate_bw function for dcn21. Signed-off-by:
-
Sung Lee authored
[WHY] DF PState and Voltage State are coupled such that one cannot be raised without raising the other. This uses more power than is necessary in high bandwidth scenarios. [HOW] Add logic to create a new bounding box state that allows for DF PState to be low while Voltage State is high. Watermarks vlevel calculation logic was also udpated to assume state 1 contains the new optimized state. Signed-off-by:
-
Christian König authored
Merge the functionality mostly into amdgpu_vm_bo_update_mapping. This way we can even handle small contiguous system pages without to much extra CPU overhead. v2: fix typo, keep the cursor as it is for now Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by: Madhav Chauhan <madhav.chauhan@amd.com> (v1) Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
-
Christian König authored
Ideally this should be a multiple of the VM block size. 2MB should at least fit for Vega/Navi. Signed-off-by:
Madhav Chauhan <madhav.chauhan@amd.com> Reviewed-by:
-
Tao Zhou authored
Per PMFW 59.9.0. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
-
John Clements authored
loaded fw can be queried from sys fs interface Reviewed-by:
John Clements <john.clements@amd.com> Signed-off-by:
-
Xiaomeng Hou authored
enable IP discovery for vangogh. Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
Xiaomeng Hou <Xiaomeng.Hou@amd.com> Signed-off-by:
-
- 23 Oct, 2020 15 commits
-
-
David Galiffi authored
[why] get_pixel_clk_frequency_100hz is undefined in clock_source_funcs. [how] set function pointer: ".get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz" Signed-off-by:
David Galiffi <David.Galiffi@amd.com> Reviewed-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by:
-
xinhui pan authored
Size is page count here. Reviewed-by:
xinhui pan <xinhui.pan@amd.com> Signed-off-by:
-
Mauro Carvalho Chehab authored
dm_comressor_info -> dm_compressor_info The kernel-doc markup is right, but the struct itself and their references contain a typo. Signed-off-by:
Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Signed-off-by:
-
Mauro Carvalho Chehab authored
Some functions have different names between their prototypes and the kernel-doc markup. Acked-by:
-
Mauro Carvalho Chehab authored
A kernel-doc markup can't be mixed with a random comment, as it causes parsing problems. While here, change an invalid kernel-doc markup into a common comment. Acked-by:
-
Harish Kasiviswanathan authored
Workaround to fix the soft hang observed in certain compute applications. Acked-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by:
-
Madhav Chauhan authored
2MB area is reserved at top inside VM. Suggested-by:
-
Bhawanpreet Lakha authored
Enable Memory Access at Last Level (MALL) feature for display. v2: squash in 64 bit division fixes Signed-off-by:
-
Likun Gao authored
Enable Memory Access at Last Level (MALL) feature for sienna_cichlid. v2: drop module option. We need to add UAPI so userspace can request MALL per buffer. Reviewed-by:
Likun Gao <Likun.Gao@amd.com> Reviewed-by:
-
Alex Deucher authored
This adds the NOALLOC registers. Signed-off-by: -
Tom Rix authored
A break is not needed if it is preceded by a return or break Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Acked-by:
Tom Rix <trix@redhat.com> Signed-off-by:
-
Tianci.Yin authored
Reviewed-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
Tianci.Yin <tianci.yin@amd.com> Signed-off-by:
-
Tianci.Yin authored
The blockchain SKU has no display and video support, remove them. Reviewed-by:
-
Likun Gao authored
Skip disabled sa to correct the cu_info and active_rbs for sienna cichlid. Signed-off-by:
-
Kenneth Feng authored
if it's fine-grained clock dpm, remove the average clock value and reflects the real clock. Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
-
