- 29 Nov, 2023 40 commits
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Lijo Lazar authored
The legacy region at 0x7F000 maps to valid registers in GC 9.4.3 SOCs. Use 0x1A000 offset instead as MMIO register remap region. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Lijo Lazar authored
Add support to read state of XGMI links in aquavanjaram SOC. Signed-off-by:
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Lijo Lazar authored
Add support to read aqua vanjaram PCIE register state Signed-off-by:
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Lijo Lazar authored
Add reg_state attribute to fetch the register snapshot of different IPs like XGMI, WAFL,PCIE and USR. To get a snapshot for a particular IP 1) Open the sysfs file 2) Seek to the offset as defined in amdgpu_sysfs_reg_offset 3) Read Signed-off-by:
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Alex Deucher authored
This header defines the reg state structures exposed via sysfs for umr debugging. v2: add content type Signed-off-by:
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Aric Cyr authored
This version brings along following fixes: - Add DSC granular throughput adjustment - Allow DTBCLK disable for DCN35 - Update Fixed VS/PE Retimer Sequence - Block dcn315 dynamic crb allocation when unintended - Update dcn315 lpddr pstate latency - Fix some HostVM parameters in DML Reviewed-by:
Tom Chung <chiahsuan.chung@amd.com> Acked-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Taimur Hassan authored
[Why] A number of DML parameters related to HostVM were either missing or being set incorrectly, which may cause inaccuracies in calculating margins and determining BW limitations. [How] Correct these values where needed and populate the missing values. Cc: stable@vger.kernel.org Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
Taimur Hassan <syed.hassan@amd.com> Signed-off-by:
Roman Li <Roman.Li@amd.com> Tested-by:
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Ilya Bakoulin authored
[Why/How] Update DSC DPCD parsing to take granular throughput adjustment into consideration. Reviewed-by:
Wenjing Liu <wenjing.liu@amd.com> Acked-by:
Ilya Bakoulin <ilya.bakoulin@amd.com> Tested-by:
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ZhenGuo Yin authored
[Why] Memory leaks of gang_ctx_bo and wptr_bo. [How] Free gang_ctx_bo and wptr_bo in pqm_uninit. v2: add a common function pqm_clean_queue_resource to free queue's resources. v3: reset pdd->pqd.num_gws when destorying GWS queue. Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
ZhenGuo Yin <zhenguo.yin@amd.com> Signed-off-by:
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Candice Li authored
Check smu v13_0_0 SKU type to select EEPROM I2C address. Signed-off-by:
Candice Li <candice.li@amd.com> Reviewed-by:
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Nicholas Kazlauskas authored
[Why] DTBCLK is enabled on idle and it will burn power. [How] There's a few issues here: - Always enabling DTBCLK on clock manager init - Setting refclk when DTBCLK is supposed to be disabled - Not applying the correct calculated version refclk, but instead the base value which might be zero On dtbclk_en change we'll message PMFW to enable or disable the clock accordingly. The DTBDTO will be then based on refclk, but it will be set to the default fixed value if there was nothing calculated in DML despite the clock being considered enabled. Reviewed-by:
Charlene Liu <charlene.liu@amd.com> Acked-by:
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Anthony Koo authored
- Add a new dmub command in enum dmub_cmd_cab_type Reviewed-by:
Anthony Koo <anthony.koo@amd.com> Tested-by:
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Felix Kuehling authored
Make restore workers freezable so we don't have to explicitly flush them in suspend and GPU reset code paths, and we don't accidentally try to restore BOs while the GPU is suspended. Not having to flush restore_work also helps avoid lock/fence dependencies in the GPU reset case where we're not allowed to wait for fences. A side effect of this is, that we can now have multiple concurrent threads trying to signal the same eviction fence. Rework eviction fence signaling and replacement to account for that. The GPU reset path can no longer rely on restore_process_worker to resume queues because evict/restore workers can run independently of it. Instead call a new restore_process_helper directly. This is an RFC and request for testing. v2: - Reworked eviction fence signaling - Introduced restore_process_helper v3: - Handle unsignaled eviction fences in restore_process_bos Signed-off-by:
Christian König <christian.koenig@amd.com> Tested-by:
Emily Deng <Emily.Deng@amd.com> Signed-off-by:
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Michael Strauss authored
[WHY/HOW] Add a new AUX sequence provided by vendor to improve interop with specific display configurations. Reviewed-by:
Michael Strauss <michael.strauss@amd.com> Tested-by:
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Dmytro Laktyushkin authored
[WHY/HOW] Limit the dynamic crb to dual stream configs that include eDP Reviewed-by:
Dmytro Laktyushkin <dmytro.laktyushkin@amd.com> Tested-by:
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Mario Limonciello authored
When dGPU is put into BOCO it may be in D3cold but still able send PME on display hotplug event. For this to work it must be enabled as wake source from D3. When runpm is enabled use pci_wake_from_d3() to mark wakeup as enabled by default. Cc: stable@vger.kernel.org # 6.1+ Signed-off-by:
Mario Limonciello <mario.limonciello@amd.com> Acked-by:
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Lu Yao authored
For 'AMDGPU_FAMILY_SI' family cards, in 'si_common_early_init' func, init 'didt_rreg' and 'didt_wreg' to 'NULL'. But in func 'amdgpu_debugfs_regs_didt_read/write', using 'RREG32_DIDT' 'WREG32_DIDT' lacks of relevant judgment. And other 'amdgpu_ip_block_version' that use these two definitions won't be added for 'AMDGPU_FAMILY_SI'. So, add null pointer judgment before calling. Reviewed-by:
Lu Yao <yaolu@kylinos.cn> Signed-off-by:
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Dinghao Liu authored
When kzalloc() for smu_table->ecc_table fails, we should free the previously allocated resources to prevent memleak. Fixes: edd79420 ("drm/amd/pm: add message smu to get ecc_table v2") Signed-off-by:
Dinghao Liu <dinghao.liu@zju.edu.cn> Signed-off-by:
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Alex Deucher authored
This worked by luck if the GART aperture ended up at 0. When we ended up moving GART on some chips, the GART aperture ended up offsetting the AGP address since the resource->start is a GART offset, not an MC address. Fix this by moving the AGP address setup into amdgpu_bo_gpu_offset_no_check(). v2: check mem_type before checking agp v3: check if the ttm bo has a ttm_tt allocated yet Fixes: 67318cb8 ("drm/amdgpu/gmc11: set gart placement GC11") Tested-by:
Jesse Zhang <Jesse.Zhang@amd.com> Reported-by:
Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by:
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RutingZhang authored
checkpatch complains that: WARNING: braces {} are not necessary for single statement blocks + if (pool->base.irqs != NULL) { + dal_irq_service_destroy(&pool->base.irqs); + } Fixed it by removing unnecessary braces to fix the coding style issue. Signed-off-by:RutingZhang <u202112078@hust.edu.cn> Reviewed-by:
Dongliang Mu <dzm91@hust.edu.cn> Signed-off-by:
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Dmytro Laktyushkin authored
[WHY/HOW] Increase the pstate latency to improve ac/dc transition Reviewed-by:
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Hamza Mahfooz authored
On recent versions of DMUB firmware, if we want to completely disable ABM we have to pass ABM_LEVEL_IMMEDIATE_DISABLE as the requested ABM level to DMUB. Otherwise, LCD eDP displays are unable to reach their maximum brightness levels. So, to fix this whenever the user requests an ABM level of 0 pass ABM_LEVEL_IMMEDIATE_DISABLE to DMUB instead. Also, to keep the user's experience consistent map ABM_LEVEL_IMMEDIATE_DISABLE to 0 when a user tries to read the requested ABM level. Cc: stable@vger.kernel.org # 6.1+ Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Lijo Lazar authored
Refactor code such that ras block decides the default mca debug mode, and not swsmu block. By default mca debug mode is set to false. v2: squash in uninitialized value fix (Alex) Signed-off-by:
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Aric Cyr authored
This version brings along the following: - DCN314 fixes - DCN32 fixes - DCN35 fixes - DML2 fixes - eDP fixes - HDR fixes - MST fixes - Replay fixes - SubVP support for more configs Acked-by:
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Anthony Koo authored
- Add a tracing framework, to measure duration, execution count and longest duration of main loop/vsync interrupt work GPINT command is used to start/stop the measurements. Acked-by:
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Sung Joon Kim authored
[why] We have dynamic power control in driver but should be ignored when power is forced on. [how] Bypass any power control when it's forced on. Cc: stable@vger.kernel.org Reviewed-by:
Sung Joon Kim <sungkim@amd.com> Signed-off-by:
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Taimur Hassan authored
[Why] There are a number of instances where we convert HostVMMinPageSize or GPUVMMinPageSize from bytes to KB by dividing (rather than multiplying) and vice versa. Additionally, in some cases, a parameter is passed through DML in KB but later checked as if it were in bytes. Cc: stable@vger.kernel.org Reviewed-by:
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Mukul Joshi authored
KFD_GC_VERSION was recently updated to use a new function for IP version checks. As a result, use KFD_GC_VERSION as the common function for all IP version checks in KFD. Signed-off-by:
Mukul Joshi <mukul.joshi@amd.com> Reviewed-by:
Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by:
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Taimur Hassan authored
[Why] Prevent overwrite of dc->config.use_default_clock_table, as it should be pre-configured. Reviewed-by:
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Nicholas Kazlauskas authored
[Why] The new table doesn't have an implicit mapping between Fclk SOC voltage and MemClk and it currently builds the table off of number of Fclk states rather than DcfClock states. The DML table in use is not correct for functionality or power and does not align with our existing policies for DCN3x. [How] Build the table based on DcfClock with the following assumptions: 1. Raising Soc voltage is the most expensive operation, so assume that running at max DispClock or DppClock is preferable. 2. Assume that we can run at max Fclk / MemClk at any state, but restrict the maximum state to the very last entry in the table as the worst case scenario. 3. Assume that Fclk always has a 2x multiplier on DcfClock unless the table specifies something lower. Reviewed-by:
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Parandhaman K authored
[why] Move all optc files to unique folder optc. [how] creating optc repo in dc, and moved the dcnxx_optc.c and .h files into corresponding new folders inside the optc and cleared the linkage errors by adding relative paths in the Makefile.template. Reviewed-by:
Martin Leung <martin.leung@amd.com> Acked-by:
Parandhaman K <parandhaman.k@amd.com> Signed-off-by:
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Zhongwei authored
[WHY] Handover from DMUB to driver does not perform link rate toggle. It might cause link training failure for boot up. [HOW] Force toggle rate wa for first link train. link->vendor_specific_lttpr_link_rate_wa should be zero then. Cc: stable@vger.kernel.org # 6.1+ Reviewed-by:
Zhongwei <zhongwei.zhang@amd.com> Signed-off-by:
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Alvin Lee authored
[Description] - To reduce vlevel further, we can try to apply subvp on configs that already support p-state since the natural p-state support may not allow for DPM0. - Add code to try subvp to reduce UCLK DPM level further if already supported, but don't use subvp if it does not optimize the DPM level even lower Reviewed-by:
Samson Tam <samson.tam@amd.com> Acked-by:
Alvin Lee <alvin.lee2@amd.com> Signed-off-by:
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Prike Liang authored
Fix the amdgpu runpm dereference usage count. Signed-off-by:
Prike Liang <Prike.Liang@amd.com> Reviewed-by:
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Gabe Teeger authored
This reverts commit fcfc6cee. [why] Flickering observed. Regression search pointed to this being the offending commit. Reviewed-by:
Yihan Zhu <yihan.zhu@amd.com> Acked-by:
Gabe Teeger <gabe.teeger@amd.com> Signed-off-by:
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Nicholas Kazlauskas authored
[Why] Some panels with residency period of 2054 exhibit flickering with Z8 at the end of the frame. [How] As a workaround, increase the limit to block these panels. Cc: stable@vger.kernel.org # 6.1+ Reviewed-by:
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Nicholas Kazlauskas authored
[Why] Flickering occurs on DRR supported panels when engaged in DRR due to min_dst_y_next becoming larger than the frame size itself. [How] In general, we should be able to enter Z8 when this is engaged but it might be a net power loss even if the calculation wasn't bugged. Don't support enabling Z8 during the DRR region. Cc: stable@vger.kernel.org # 6.1+ Reviewed-by:
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Meenakshikumar Somasundaram authored
[Why] When otg workaround is applied during clock update, otgs of tiled display went out of sync. [How] To call dc_trigger_sync() after clock update to sync otgs again. Reviewed-by:
Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Signed-off-by:
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Tim Huang authored
Fix a memory overflow issue in the gfx IB test for some ASICs. At least 20 bytes are needed for the IB test packet. v2: correct code indentation errors. (Christian) Signed-off-by:
Tim Huang <Tim.Huang@amd.com> Reviewed-by:
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Li Ma authored
enable init_registers callback func for nbio v7.11. Signed-off-by:
Li Ma <li.ma@amd.com> Reviewed-by:
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