- 03 Sep, 2015 40 commits
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Markos Chandras authored
MIPS R6 introduced the following instruction: Stores in fd a bit mask reflecting the floating-point class of the floating point scalar value fs. CLASS.fmt: FPR[fd] = class(FPR[fs]) Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10959/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Markos Chandras authored
MIPS R6 introduced the following instruction: Floating-Point Round to Integral Scalar floating-point round to integral floating point value. RINT.fmt: FPR[fd] = round_int(FPR[fs]) Signed-off-by:
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Markos Chandras authored
MIPS R6 introduced the following instruction: Floating Point Fused Multiply Subtract: MSUBF.fmt To perform a fused multiply-subtract of FP values. MSUBF.fmt: FPR[fd] = FPR[fd] - (FPR[fs] x FPR[ft]) Signed-off-by:
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Markos Chandras authored
MIPS R6 introduced the following instruction: Floating Point Fused Multiply Add: MADDF.fmt To perform a fused multiply-add of FP values. MADDF.fmt: FPR[fd] = FPR[fd] + (FPR[fs] x FPR[ft]) Signed-off-by:
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Markos Chandras authored
MIPS R6 introduced the following instruction: SELNEZ.fmt: FPR[fd] FPR[ft].bit0 ? FPR[fs] : 0 Add support for emulating the single and double precision formats of the said instruction. Signed-off-by:
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Markos Chandras authored
MIPS R6 introduced the following instruction: SELEQZ.fmt: FPR[fd] FPR[ft].bit0 ? 0 : FPR[fs] Add support for emulating the single and double precision formats of the said instruction. Signed-off-by:
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Markos Chandras authored
Add support for emulating the new CMP.condn.fmt R6 instructions and return SIGILL for the old C.cond.fmt if R2 emulation is not enabled since it's not supported by R6. The functionality of the new CMP.condn.fmt is the following one: If the comparison specified by the condn field of the instruction is true for the operand values, the result is true; otherwise, the result is false. If no exception is taken, the result is written into FPR fd; true is all 1s and false is all 0s repeated the operand width of fmt. All other bits beyond the operand width fmt are UNPREDICTABLE. Signed-off-by:
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Markos Chandras authored
Add opcodes for the new MIPS R6 FPU instructions. Signed-off-by:
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Aaro Koskinen authored
Management port MII address is incorrect on Kontron S1901 resulting in broken networking. Fix by providing definitions for the in-tree DT pruning code. Signed-off-by:
Aaro Koskinen <aaro.koskinen@nokia.com> Acked-by:
David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10914/Signed-off-by:
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Andrzej Hajda authored
The patch was generated using fixed coccinelle semantic patch scripts/coccinelle/api/memdup.cocci [1]. [1]: http://permalink.gmane.org/gmane.linux.kernel/2014320Signed-off-by:
Andrzej Hajda <a.hajda@samsung.com> Acked-by:
Hauke Mehrtens <hauke@hauke-m.de> Cc: Hauke Mehrtens <hauke@hauke-m.de> Cc: Rafał Miłecki <zajec5@gmail.com> Cc: Andrzej Hajda <a.hajda@samsung.com> Cc: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Cc: Marek Szyprowski <m.szyprowski@samsung.com> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10898/Signed-off-by:
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Janne Huttunen authored
Currently the Octeon Ethernet driver hardcodes the mapping between interface/port and IPD port number. Since we have generic helpers for the very same purpose, we might as well use them instead. This prevents having the same information in multiple places. Signed-off-by:
Janne Huttunen <janne.huttunen@nokia.com> Signed-off-by:
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Janne Huttunen authored
Add the support for mapping between interface/port numbers and IPD port numbers also for the additional interfaces some Octeon II models have. Signed-off-by:
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Janne Huttunen authored
Use the internal port number also as the queue number on CN68XX. Signed-off-by:
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Janne Huttunen authored
CN68XX requires a different PKO configuration. This patch provides just enough setup to get the XAUI interfaces on CN6880 working with default parameters. Signed-off-by:
Janne Huttunen <janne.huttunen@nsn.com> Signed-off-by:
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Janne Huttunen authored
CN68XX has a bit different WQE structure. This patch provides the new definitions and converts the code to use the proper variant based on the actual model. Signed-off-by:
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Janne Huttunen authored
The Octeon II models have more interfaces and thus require more output command buffers. Increase the allocation to support these models. Signed-off-by:
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Aaro Koskinen authored
CN68XX uses SSO instead of POW. Signed-off-by:
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Aaro Koskinen authored
The Octeon models with SSO instead of POW need to use a different register for configuring the WQE interrupt thresholds. Signed-off-by:
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Janne Huttunen authored
Some Octeon II models have SSO instead of POW and use a different register for setting the interrupt thresholds. Add the necessary definitions for configuring the interrupts also on those models. Signed-off-by:
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Janne Huttunen authored
CN68XX has common minimum packet size filters that need to be configured for the traffic to work. Just set them to a default value. Signed-off-by:
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Janne Huttunen authored
Configure the pkinds of XAUI interfaces on Octeon models that have them. This simple configuration uses 1:1 mapping between the PIP input port number and the selected pkind. Signed-off-by:
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Janne Huttunen authored
CN68XX has 48 PIP input ports. Signed-off-by:
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Janne Huttunen authored
CN68XX has 9 interfaces. Signed-off-by:
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Janne Huttunen authored
Some CN68XX series Octeon II chips seem to hang if a reset is issued on XAUI initialization. Avoid the hang by disabling the reset on affected models. Tested on Cavium EBB6800 evaluation board and Kontron S1901 board. Signed-off-by:
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Ezequiel Garcia authored
This commit introduces a new config, so the user can choose to enable the General Purpose Timer based clocksource. This option is required to have CPUFreq support. Signed-off-by:
Ezequiel Garcia <ezequiel.garcia@imgtec.com> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: devicetree@vger.kernel.org Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: James Hartley <James.Hartley@imgtec.com> Cc: Govindraj Raja <Govindraj.Raja@imgtec.com> Cc: Damien Horsley <Damien.Horsley@imgtec.com> Cc: James Hogan <James.Hogan@imgtec.com> Cc: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Cc: Ezequiel Garcia <ezequiel.garcia@imgtec.com> Patchwork: http://patchwork.linux-mips.org/patch/10887/Signed-off-by:
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Ezequiel Garcia authored
The Pistachio SoC provides four general purpose timers, and allow to implement a clocksource driver. This driver can be used as a replacement for the MIPS GIC and MIPS R4K clocksources and sched clocks, which are clocked from the CPU clock. Given the general purpose timers are clocked from an independent clock, this new clocksource driver will be useful to introduce CPUFreq support for Pistachio machines. Signed-off-by:
Govindraj Raja <govindraj.raja@imgtec.com> Reviewed-by:
Thomas Gleixner <tglx@linutronix.de> Acked-by:
Daniel Lezcano <daniel.lezcano@linaro.org> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: Andrew Bresticker <abrestic@chromium.org> Cc: James Hartley <James.Hartley@imgtec.com> Cc: Damien Horsley <Damien.Horsley@imgtec.com> Cc: James Hogan <James.Hogan@imgtec.com> Cc: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Cc: Ezequiel Garcia <ezequiel.garcia@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/10899/Signed-off-by:
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Ezequiel Garcia authored
Add a device-tree binding document for the clocksource driver provided by Pistachio SoC general purpose timers. Signed-off-by:
Andrew Bresticker <abrestic@chromium.org> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: devicetree@vger.kernel.org Cc: Thomas Gleixner <tglx@linutronix.de> Cc: James Hartley <James.Hartley@imgtec.com> Cc: Govindraj Raja <Govindraj.Raja@imgtec.com> Cc: Damien Horsley <Damien.Horsley@imgtec.com> Cc: James Hogan <James.Hogan@imgtec.com> Cc: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Patchwork: https://patchwork.linux-mips.org/patch/10783/Signed-off-by:
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Ezequiel Garcia authored
This commit introduces the clockevent frequency update, using a clock notifier. It will be used to support CPUFreq on platforms using MIPS GIC based clockevents. Signed-off-by:
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Guenter Roeck authored
Now that we're ready to enable COMMON_CLK for GIC platforms do so for Malta and SEAD3. The only other user of the GIC Pistachio does already do so. [ralf@linux-mips.org: Rewrite the commit message because applied in the right order there is no breakage thus no fix required.] Signed-off-by:
Guenter Roeck <linux@roeck-us.net> Cc: Ezequiel Garcia <ezequiel.garcia@imgtec.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11038/Signed-off-by:
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Ezequiel Garcia authored
This is preparation work for the introduction of clockevent frequency update with a clock notifier. This is only possible when the device is passed a clk struct, so let's split the legacy and devicetree initialization. Reviewed-by:
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Ezequiel Garcia authored
This commit adds the required checks on the functions that return an error. Some of them are not critical, so only a warning is printed. Signed-off-by:
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Ezequiel Garcia authored
For the clock to be used (e.g. get its rate through clk_get_rate) it should be prepared and enabled first. Also, while the clock is enabled the driver must hold a reference to it, so let's remove the call to clk_put. Reviewed-by:
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Paul Burton authored
Rather than saving the scalar FP or vector context in the assembly resume function, reuse the existing C code we have in fpu.h to do exactly that. This reduces duplication, results in a much easier to read resume function & should allow the compiler to optimise out more MSA code due to is_msa_enabled()/cpu_has_msa being known-zero at compile time for kernels without MSA support. Signed-off-by:
Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-kernel@vger.kernel.org Cc: James Hogan <james.hogan@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Manuel Lauss <manuel.lauss@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/10830/Signed-off-by:
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Antonio Ospite authored
Fix the 0x0x prefix in integer constants, in this case the registers interval is actually 0x8065 .. 0x80A4 as confirmed some lines above in the code. Signed-off-by:
Antonio Ospite <ao2@ao2.it> Cc: linux-mips@linux-mips.org Cc: Jiri Kosina <trivial@kernel.org> Patchwork: https://patchwork.linux-mips.org/patch/9908/Signed-off-by:
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Ralf Baechle authored
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Ralf Baechle authored
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Ralf Baechle authored
This reverts commit 7281cd22 and adds actual functionality to use the field.
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Subhendu Sekhar Behera authored
Add NAND IRQ mapping for XLP9xx processor. Signed-off-by:
Subhendu Sekhar Behera <sbehera@broadcom.com> Signed-off-by:
Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10820/Signed-off-by:
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Kamlakant Patel authored
This is needed to enable GPIO framework support for Netlogic XLP platform. Signed-off-by:
Kamlakant Patel <kamlakant.patel@broadcom.com> Signed-off-by:
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Kamlakant Patel authored
Add GPIO entries to the Netlogic XLP device tree files. Signed-off-by:
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