- 23 Dec, 2007 24 commits
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Valentine Barshak authored
PowerPC 440GRx Rainier DTS. Signed-off-by:
Valentine Barshak <vbarshak@ru.mvista.com> Signed-off-by:
Josh Boyer <jwboyer@linux.vnet.ibm.com>
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Valentine Barshak authored
Bootwrapper code for PowerPC 440GRx Rainier board. Signed-off-by:
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Valentine Barshak authored
Add the 440EPx Sequoia USB OHCI device tree entry. Signed-off-by:
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Stefan Roese authored
This patch adds runtime detection of the 440SPe revision A chips. These chips are equipped with a slighly different PCIe core and need special/ different initialization. The compatible node is changed to "plb-pciex-440spe" ("A" and "B" dropped). This is needed for boards that can be equipped with both PPC revisions like the AMCC Yucca. Signed-off-by:Stefan Roese <sr@denx.de> Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by:
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Benjamin Herrenschmidt authored
This makes 4xx embedded platforms re-assign all PCI resources as we pretty much never care about what the various firmwares have done on these, it's generally not compatible with the way the kernel will map the bridges. We still need to also enable bus renumbering on some of them, but I will do that from a separate patch after I've fixed 4xx PCIe to handle all bus numbers. Signed-off-by:
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Benjamin Herrenschmidt authored
This improves the way the 4xx PCI-E code handles checking for a link and adds explicit testing of CRS result codes on config space accesses. This should make it more reliable. Also, bridges with no link are now still created, though config space accesses beyond the root complex are filtered. This is one step toward eventually supporting hotplug. Signed-off-by:
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Benjamin Herrenschmidt authored
This removes a bogus empty "ranges" property in the EBC device node of the Bamboo board device-tree. The "ranges" property should be created by the wrapper code when it is implemented. Until then, remove the empty property since it incorrectly implies that there is a 1:1 address mapping between the EBC and the OPB. This also fixes a warning from newer DTCs. Signed-off-by:
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Benjamin Herrenschmidt authored
This adds base support for the Katmai board, including PCI-X and PCI-Express (but no RTC, nvram, etc... yet). Signed-off-by:
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Benjamin Herrenschmidt authored
This reworks the boot wrapper library function that probes the chip clocks. Better separate the base function that is used on 440GX,SPe,EP,... from the uart fixups as those need different device-tree path on different processors. Also, rework the function itself based on the arch/ppc code from Eugene Surovegin which I find more readable, and which handles one more bypass case. Also handle the subtle difference between 440EP/EPx and 440SPe/GX, on the former, PerClk is derived from the PLB clock while on the later, it's derived from the OPB. Signed-off-by:
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Benjamin Herrenschmidt authored
This adds macros to the boot wrapper to access the CPR registers from the boot wrappers. Signed-off-by:
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Benjamin Herrenschmidt authored
The 4xx bootwrapper occasionally needs to access SPR registers, this adds mfspr/mtspr wrappers to it. Signed-off-by:
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Benjamin Herrenschmidt authored
This adds a function to the bootwrapper 4xx library to decode memory size on 440SPE processors. Signed-off-by:
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Benjamin Herrenschmidt authored
This adds the definition of the on-chip OHCI controller to the Bamboo board's device-tree. This is enough to get it probed and working, though a separate patch fixing a bug in the OHCI driver is needed to make it reliable. Signed-off-by:
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Benjamin Herrenschmidt authored
This adds the device-tree bits & call to ppc4xx_pci_find_bridges() to make PCI work on the Bamboo board Signed-off-by:
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Hugh Blemings authored
This patch adds base support for the AMCC Taishan 440GX evaluation board. Signed-off-by:
Hugh Blemings <hugh@blemings.org> Signed-off-by:
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Benjamin Herrenschmidt authored
This wires up the 4xx PCI support & device-tree bits for the 405GP based Walnut platform. Signed-off-by:
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Benjamin Herrenschmidt authored
Brings EP405 support to arch/powerpc. The IRQ routing for the CPLD comes from a device-tree property, PCI is working to the point where I can see the video card, USB device, and south bridge. This should work with both EP405 and EP405PC. I've not totally figured out how IRQs are wired on this hardware though, thus at this stage, expect only USB interrupts working, pretty much the same as what arch/ppc did. Also, the flash, nvram, rtc and temp control still have to be wired. Signed-off-by:
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Benjamin Herrenschmidt authored
This adds some basic real mode based early udbg support for 40x in order to debug things more easily Signed-off-by:
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Benjamin Herrenschmidt authored
This wires up the 4xx PCI support & device tree bits for 440GP based Ebony platform. Signed-off-by:
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Benjamin Herrenschmidt authored
This adds to the previous 2 patches the support for the 4xx PCI Express cells as found in the 440SPe revA, revB and 405EX. Unfortunately, due to significant differences between these, and other interesting "features" of those pieces of HW, the code isn't as simple as it is for PCI and PCI-X and some of the functions differ significantly between the 3 implementations. Thus, not only this code can only support those 3 implementations for now and will refuse to operate on any other, but there are added ifdef's to avoid the bloat of building a fairly large amount of code on platforms that don't need it. Also, this code currently only supports fully initializing root complex nodes, not endpoint. Some more code will have to be lifted from the arch/ppc implementation to add the endpoint support, though it's mostly differences in memory mapping, and the question on how to represent endpoint mode PCI in the device-tree is thus open. Many thanks to Stefan Roese for testing & fixing up the 405EX bits ! Signed-off-by:
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Benjamin Herrenschmidt authored
This adds to the previous patch the support for the 4xx PCI 2.x bridges. Signed-off-by:
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Benjamin Herrenschmidt authored
This adds base support code for the 4xx PCI-X bridge. It also provides placeholders for the PCI and PCI-E version but they aren't supported with this patch. The bridges are configured based on device-tree properties. Signed-off-by:
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Benjamin Herrenschmidt authored
Accessing indirect DCRs is done via a pair of address/data DCRs. Such accesses are thus inherently racy, vs. interrupts, preemption and possibly SMP if 4xx SMP cores are ever used. This updates the mfdcri/mtdcri macros in dcr-native.h (which were so far unused) to use a spinlock. In addition, add some common definitions to a new dcr-regs.h file. Signed-off-by:
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Benjamin Herrenschmidt authored
This adds a cputable function pointer for the CPU-side machine check handling. The semantic is still the same as the old one, the one in ppc_md. overrides the one in cputable, though ultimately we'll want to change that so the CPU gets first. This removes CONFIG_440A which was a problem for multiplatform kernels and instead fixes up the IVOR at runtime from a setup_cpu function. The "A" version of the machine check also tweaks the regs->trap value to differenciate the 2 versions at the C level. Signed-off-by:
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- 21 Dec, 2007 16 commits
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Paul Mackerras authored
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Stephen Rothwell authored
Maple and pasemi both require PCI as does CONFIG_OF_PLATFORM_PCI. The default setting of CONFIG_ISA_DMA_API is set to match the protection around the relevant routines in asm/dma.h. I also had to remove the PMAC platform from the combined build. The precis is that to build a 64 bit kernel with no PCI, you can only include pSeries and iSeries. Signed-off-by:
Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by:
Paul Mackerras <paulus@samba.org>
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Stephen Rothwell authored
Fixes this warning: arch/powerpc/platforms/powermac/pci.c: In function 'u3_ht_cfg_access': arch/powerpc/platforms/powermac/pci.c:354: warning: return discards qualifiers from pointer target type arch/powerpc/platforms/powermac/pci.c:358: warning: return discards qualifiers from pointer target type Signed-off-by:
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Stephen Rothwell authored
This will allow us to declare const all the statically declared arrrays of these. Signed-off-by:
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Stephen Rothwell authored
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Stephen Rothwell authored
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Benjamin Herrenschmidt authored
The 32-bit PCI code tests if "bus" is non-NULL after calling pci_scan_bus_parented() in one place but not another before dereferencing it. Signed-off-by:
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Benjamin Herrenschmidt authored
This fixes a few issues with via-pmu based backlight control. First, it fixes a sign problem with the setup of the backlight curve since the `range' value there -can- (and will) go negative. Then, it reworks the interaction between this and the via-pmu sleep code to properly restore backlight on wakeup from sleep. Signed-off-by:
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Scott Wood authored
These hooks ensure that a decrementer interrupt is not pending when suspending; otherwise, problems may occur on 6xx/7xx/7xxx-based systems (except for powermacs, which use a separate suspend path). For example, with deep sleep on the 831x, a pending decrementer will cause a system freeze because the SoC thinks the decrementer interrupt would have woken the system, but the core must have interrupts disabled due to the setup required for deep sleep. Changed via-pmu.c to use the new ppc_md hooks, and made the arch_* functions call the generic_* functions unconditionally. -- paulus Signed-off-by:
Scott Wood <scottwood@freescale.com> Signed-off-by:
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Jeremy Kerr authored
Based on an original patch from Arnd Bergmann <arnd.bergmann@de.ibm.com> If there's no entry in the mailbox, then a read on the _info file will return data from an uninitialised variable. This change returns EOF if there's no mailbox info available instead. Signed-off-by:
Jeremy Kerr <jk@ozlabs.org> Signed-off-by:
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Andre Detsch authored
This fixes the behavior of spufs when a spu tries a DMA operation based on a wrong / unavailable address. Instead of just generating a SIGBUS signal, spufs now generates a SIGSEGV signal and restarts the problematic DMA operation after the execution of the application's signal handler. This allows applications to employ user-level paging systems. Although the restart_dma function is called before the application's signal handler, the operation is not actually performed at this time, since the spu context is already stopped. The operation only takes place when spu_run is restarted (which happens automatically). Signed-off-by:
Andre Detsch <adetsch@br.ibm.com> Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
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Aegis Lin authored
The original spusched_timer was designed to take effect only when a context is waiting in the runqueue. This change adds an additional lower-freq timer has been added to purely handle the spu_load updates. The new timer will be triggered per LOAD_FREQ ticks. Signed-off-by:
Aegis Lin <aegislin@gmail.com> Signed-off-by:
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Christoph Hellwig authored
Make most places that use spu_acquire/spu_acquire_saved interruptible, this allows getting out of the spufs code when e.g. pressing ctrl+c. There are a few places where we get called e.g. from spufs teardown routines were we can't simply err out so these are left with a comment. For now I've also not touched the poll routines because it's open what libspe would expect in terms of interrupted system calls. Acked-by:
Arnd Bergmann <arnd.bergmann@de.ibm.com> Signed-off-by:
Christoph Hellwig <hch@lst.de> Signed-off-by:
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Christoph Hellwig authored
The simple attr macros currently used by spufs can't deal with the handlers returning errors, which is required to make the state_mutex interruptible. This adds a local copy that allows for an error return from the get/set handlers. Signed-off-by:
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Luke Browning authored
Change spufs_spu_run so that the context is queued directly to the scheduler and the controlling thread advances directly to spufs_wait() for spe errors and exceptions. nosched contexts are treated the same as before. Fixes from Christoph Hellwig <hch@lst.de> Signed-off-by:
Luke Browning <lukebr@linux.vnet.ibm.com> Signed-off-by:
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Masato Noguchi authored
This changes the spu context switch code to not write to reserved bits of spu interrupt status register. The architecture book says the reserved fields should be set to zero. Signed-off-by:
Masato Noguchi <Masato.Noguchi@jp.sony.com> Signed-off-by:
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