- 08 Jun, 2021 33 commits
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Wesley Chalmers authored
[WHY] HW has handed down a new sequence that requires access to these registers. v2: squash in DCN3.1 fixes (Alex) Signed-off-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
Stylon Wang <stylon.wang@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Wesley Chalmers authored
[WHY] HW has handed down a new sequence which requires access to the FIFO ERRDET SW Override register. Signed-off-by:
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Aric Cyr authored
Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
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Anthony Koo authored
Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Aric Cyr authored
[Why] Rearranging pipes with multiple displays and multiple planes cannot be done atomically and requires a much improved sequence to deal with it. [How] To workaround such issues, prefer avoid pipe-split policy for multidisplay scenarios. Signed-off-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by:
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Vladimir Stempen authored
[why] When OS overrides training link training parameters for MST device to SST mode, MST resources are not released and leak of the resource may result crash and incorrect MST discovery during following hot plugs. [how] Retaining sink object to be reused by SST link and releasing MST resources. Signed-off-by:
Vladimir Stempen <vladimir.stempen@amd.com> Reviewed-by:
Wenjing Liu <Wenjing.Liu@amd.com> Acked-by:
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Mikita Lipski authored
[why] Allow specifying which panel to take PSR Residency measurements from. [how] Pass panel instance to DMUB through GPINT in the upper 8 bits of the parameter. Signed-off-by:
Mikita Lipski <mikita.lipski@amd.com> Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
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Jayendran Ramani authored
[How] Add call to get the last used VTOTAL from DC Signed-off-by:
Jayendran Ramani <Jayendran.Ramani@amd.com> Reviewed-by:
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Meenakshikumar Somasundaram authored
[Why & How] SET_CONFIG transactions with DMUB is not used and removed. Signed-off-by:
Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Roman Li authored
[Why] We update scaling settings when scaling mode has been changed. However when changing mode from native resolution the scaling mode previously set gets ignored. [How] Perform scaling settings update on modeset. Signed-off-by:
Roman Li <roman.li@amd.com> Reviewed-by:
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Jimmy Kizito authored
[Why & How] Add support for transmitting training pattern sequences for links whose encoders have been dynamically assigned. Signed-off-by:
Jimmy Kizito <Jimmy.Kizito@amd.com> Reviewed-by:
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Jimmy Kizito authored
[Why & How] Add functionality useful for DP equalization phase of link training to public interface. Signed-off-by:
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Ilya Bakoulin authored
[Why] This change was found to break some high-refresh modes. Reverting to unblock mainline. Signed-off-by:
Ilya Bakoulin <Ilya.Bakoulin@amd.com> Reviewed-by:
Sung Lee <Sung.Lee@amd.com> Acked-by:
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Evgenii Krasnikov authored
[WHY] Currently there is no way to visually identify if there is one or more layers presented fullscreen on the display [HOW] Add new visual confirm colors in get_surface_visual_confirm_color for planes with layer_index > 0 Signed-off-by:
Evgenii Krasnikov <Evgenii.Krasnikov@amd.com> Reviewed-by:
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Wyatt Wood authored
[Why + How] Visual confirm has no asic-specific logic, so we can refactor and unify these functions that are currently spread out across multiple dcn files. Add a new hw sequencer interface update_visual_confirm_color, and a new mpc function pointer set_bg_color. This will allow visual confirm to updated independently of MPCC blending updates. v2: squash in DCN3.1 fixes Signed-off-by:
Wyatt Wood <wyatt.wood@amd.com> Reviewed-by:
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JinZe.Xu authored
[Why] This disablement would be specific for Nav10 and shouldn’t be propagated to the other programs. [How] Power gating is controlled by driver. Signed-off-by:
JinZe.Xu <JinZe.Xu@amd.com> Reviewed-by:
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Nikola Cornij authored
[why] DSCCLK validation is not necessary because DSCCLK is derrived from DISPCLK, therefore if DISPCLK validation passes, DSCCLK is valid, too. Doing DSCLK validation in addition to DISPCLK leads to modes being wrongly rejected when DSCCLK was incorrectly set outside of DML. [how] Remove DSCCLK validation because it's implicitly validated under DISPCLK Signed-off-by:
Nikola Cornij <nikola.cornij@amd.com> Reviewed-by:
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Wenjing Liu authored
[why] Some DPRX will issue CP_IRQ when user disconnects a display that has been authenticated. Since display is being disconnecting dpcd read will fail. This will cause us to attempt HDCP retry on disconnection. We are adding a 100ms delay before retry. So we will only start retry if within 100ms there is no disconnection call to HDCP module. Signed-off-by:
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Mikita Lipski authored
[why] Updating PSR interfaces to allow PSR enablement per eDP panel. [how] - Copying PSR command structures to DC - Changing function interfaces to pass panel instance - Communicating with DMUB per link instead of assuming to use a single one -Iterating through all PSR capable panels when enabling/disabling all Signed-off-by:
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Jake Wang authored
[Why] During DCC on/off, stutter period is calculated before DCC has fully transitioned. This results in incorrect stutter period calculation. [How] Trigger a full update when DCC changes between on/off. Signed-off-by:
Jake Wang <haonan.wang2@amd.com> Reviewed-by:
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Zhigang Luo authored
psp added new feature to check fw buffer address for sriov vf. the address range must be in vf fb. Signed-off-by:
Zhigang Luo <zhigang.luo@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-By : Shaoyun.liu <shaoyunl@amd.com> Signed-off-by:
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Zhigang Luo authored
need to load xgmi ta for aldebaran sriov vf. Signed-off-by:
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Zhigang Luo authored
host driver programmed mmhub system aperture and fb location for vf, no need to program in guest side. Signed-off-by:
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Zhigang Luo authored
host driver programmed the gfxhub fb location for vf, no need to program in guest side. Signed-off-by:
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Zhigang Luo authored
host driver programmed fb location registers for vf, no need to check anymore. Signed-off-by:
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Xiaomeng Hou authored
Kernel test robot throws warning -> >> drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/yellow_carp_ppt.c:483:2: warning: variable 'member_type' is used uninitialized whenever switch default is taken [-Wsometimes-uninitialized] default: ^~~~~~~ drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/yellow_carp_ppt.c:487:47: note: uninitialized use occurs here return yellow_carp_get_smu_metrics_data(smu, member_type, value); ^~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/yellow_carp_ppt.c:465:2: note: variable 'member_type' is declared here MetricsMember_t member_type; ^ 1 warning generated. Fix this warning by return errno when the clk type is unsupported. Reported-by:kernel test robot <lkp@intel.com> Signed-off-by:
Xiaomeng Hou <Xiaomeng.Hou@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Acked-by:
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Nirmoy Das authored
Create shadow BOs only for no-compute VM context and only for dGPU. The existing if-condition would create shadow bo for compute context on dGPU which not what we wanted. Signed-off-by:
Nirmoy Das <nirmoy.das@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Darren Powell authored
added doc tag "amdgpu_pp_power" with description added tags for enums pp_power_limit_level, pp_power_type added tag for function smu_get_power_limit Test: * Temporary insertion into Documentation/gpu/amdgpu.rst ------------START------------ Power Limit ----------- .. kernel-doc:: drivers/gpu/drm/amd/include/kgd_pp_interface.h :doc: amdgpu_pp_power .. kernel-doc:: drivers/gpu/drm/amd/include/kgd_pp_interface.h :identifiers: pp_power_limit_level .. kernel-doc:: drivers/gpu/drm/amd/include/kgd_pp_interface.h :identifiers: pp_power_type .. kernel-doc:: drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c :identifiers: smu_get_power_limit -------------END------------- Signed-off-by:
Darren Powell <darren.powell@amd.com> Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
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Darren Powell authored
Signed-off-by:
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Darren Powell authored
modify args of smu_get_power_limit to match Powerplay API .get_power_limit add smu_get_power_limit to Powerplay API swsmu_pm_funcs remove special handling of smu in amdgpu_hwmon_show_power_cap* * Test AMDGPU_PCI_ADDR=`lspci -nn | grep "VGA\|Display" | cut -d " " -f 1` AMDGPU_HWMON=`ls -la /sys/class/hwmon | grep $AMDGPU_PCI_ADDR | cut -d " " -f 11` HWMON_DIR=/sys/class/hwmon/${AMDGPU_HWMON} lspci -nn | grep "VGA\|Display" ; \ echo "=== power1 cap ===" ; cat $HWMON_DIR/power1_cap ; \ echo "=== power1 cap max ===" ; cat $HWMON_DIR/power1_cap_max ; \ echo "=== power1 cap def ===" ; cat $HWMON_DIR/power1_cap_default Signed-off-by: -
Darren Powell authored
updated {amd_pm_funcs}->get_power_limit() signature rewrote pp_get_power_limit to use new enums pp_get_power_limit now returns -EOPNOTSUPP for unknown power limit update calls to {amd_pm_funcs}->get_power_limit() * Test Notes * testing hardware was NAVI10 (tests SMU path) ** needs testing on VANGOGH ** needs testing on SMU < 11 ** ie, one of TOPAZ, FIJI, TONGA, POLARIS10, POLARIS11, POLARIS12, VEGAM, CARRIZO, STONEY, VEGA10, VEGA12,VEGA20, RAVEN, BONAIRE, HAWAII * Test AMDGPU_PCI_ADDR=`lspci -nn | grep "VGA\|Display" | cut -d " " -f 1` AMDGPU_HWMON=`ls -la /sys/class/hwmon | grep $AMDGPU_PCI_ADDR | cut -d " " -f 11` HWMON_DIR=/sys/class/hwmon/${AMDGPU_HWMON} lspci -nn | grep "VGA\|Display" ; \ echo "=== power1 cap ===" ; cat $HWMON_DIR/power1_cap ; \ echo "=== power1 cap max ===" ; cat $HWMON_DIR/power1_cap_max ; \ echo "=== power1 cap def ===" ; cat $HWMON_DIR/power1_cap_default Signed-off-by: -
Darren Powell authored
add two new powerplay enums (limit_level, type) add enums to smu_get_power_limit signature remove input bitfield stuffing of output variable limit update calls to smu_get_power_limit * Test AMDGPU_PCI_ADDR=`lspci -nn | grep "VGA\|Display" | cut -d " " -f 1` AMDGPU_HWMON=`ls -la /sys/class/hwmon | grep $AMDGPU_PCI_ADDR | cut -d " " -f 11` HWMON_DIR=/sys/class/hwmon/${AMDGPU_HWMON} lspci -nn | grep "VGA\|Display" ; \ echo "=== power1 cap ===" ; cat $HWMON_DIR/power1_cap ; \ echo "=== power1 cap max ===" ; cat $HWMON_DIR/power1_cap_max ; \ echo "=== power1 cap def ===" ; cat $HWMON_DIR/power1_cap_default Signed-off-by: -
Darren Powell authored
Match the order of definition to the structure's declaration to help with locating included and missing functions of the API Signed-off-by:
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- 07 Jun, 2021 7 commits
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Colin Ian King authored
There are two spelling mistakes in dml_print messages, fix these and clear up checkpatch warning on overly wide line length. Signed-off-by:
Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Christophe JAILLET authored
s/than/then/ Acked-by:
Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by:
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Jiapeng Chong authored
Clean up the following includecheck warning: ./drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c: dce110_hw_sequencer.h is included more than once. No functional change. Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Signed-off-by:
Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by:
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Bernard Zhao authored
remove no need variable, just return the DC_OK Signed-off-by:
Bernard Zhao <bernard@vivo.com> Signed-off-by:
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Eric Huang authored
Add the parameter table_freed description on function description. Signed-off-by:
Eric Huang <jinhuieric.huang@amd.com> Reviewed-by:
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Wan Jiabing authored
kfd_svm.h is included duplicately in commit 42de677f ("drm/amdkfd: register svm range"). After checking possible related header files, remove the former one to make the code format more reasonable. Signed-off-by:
Wan Jiabing <wanjiabing@vivo.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Christian König authored
For GTT allocations with a GART address the res contains the VMID0 addresses and can't be used for VM handling. So ignore the res when the pages array is given or we fill the page tables with nonsense. Signed-off-by:
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