1. 04 Mar, 2022 3 commits
    • Artem Bityutskiy's avatar
      intel_idle: add core C6 optimization for SPR · 3a9cf77b
      Artem Bityutskiy authored
      Add a Sapphire Rapids Xeon C6 optimization, similar to what we have for Sky Lake
      Xeon: if package C6 is disabled, adjust C6 exit latency and target residency to
      match core C6 values, instead of using the default package C6 values.
      Signed-off-by: default avatarArtem Bityutskiy <artem.bityutskiy@linux.intel.com>
      Signed-off-by: default avatarRafael J. Wysocki <rafael.j.wysocki@intel.com>
      3a9cf77b
    • Artem Bityutskiy's avatar
      intel_idle: add 'preferred_cstates' module argument · da0e58c0
      Artem Bityutskiy authored
      On Sapphire Rapids Xeon (SPR) the C1 and C1E states are basically mutually
      exclusive - only one of them can be enabled. By default, 'intel_idle' driver
      enables C1 and disables C1E. However, some users prefer to use C1E instead of
      C1, because it saves more energy.
      
      This patch adds a new module parameter ('preferred_cstates') for enabling C1E
      and disabling C1. Here is the idea behind it.
      
      1. This option has effect only for "mutually exclusive" C-states like C1 and
         C1E on SPR.
      2. It does not have any effect on independent C-states, which do not require
         other C-states to be disabled (most states on most platforms as of today).
      3. For mutually exclusive C-states, the 'intel_idle' driver always has a
         reasonable default, such as enabling C1 on SPR by default. On other
         platforms, the default may be different.
      4. Users can override the default using the 'preferred_cstates' parameter.
      5. The parameter accepts the preferred C-states bit-mask, similarly to the
         existing 'states_off' parameter.
      6. This parameter is not limited to C1/C1E, and leaves room for supporting
         other mutually exclusive C-states, if they come in the future.
      
      Today 'intel_idle' can only be compiled-in, which means that on SPR, in order
      to disable C1 and enable C1E, users should boot with the following kernel
      argument: intel_idle.preferred_cstates=4
      Signed-off-by: default avatarArtem Bityutskiy <artem.bityutskiy@linux.intel.com>
      Signed-off-by: default avatarRafael J. Wysocki <rafael.j.wysocki@intel.com>
      da0e58c0
    • Artem Bityutskiy's avatar
      intel_idle: add SPR support · 9edf3c0f
      Artem Bityutskiy authored
      Add Sapphire Rapids Xeon support.
      
      Up until very recently, the C1 and C1E C-states were independent, but this
      has changed in some new chips, including Sapphire Rapids Xeon (SPR). In these
      chips the C1 and C1E states cannot be enabled at the same time. The "C1E
      promotion" bit in 'MSR_IA32_POWER_CTL' also has its semantics changed a bit.
      
      Here are the C1, C1E, and "C1E promotion" bit rules on Xeons before SPR.
      
      1. If C1E promotion bit is disabled.
         a. C1  requests end up with C1  C-state.
         b. C1E requests end up with C1E C-state.
      2. If C1E promotion bit is enabled.
         a. C1  requests end up with C1E C-state.
         b. C1E requests end up with C1E C-state.
      
      Here are the C1, C1E, and "C1E promotion" bit rules on Sapphire Rapids Xeon.
      1. If C1E promotion bit is disabled.
         a. C1  requests end up with C1 C-state.
         b. C1E requests end up with C1 C-state.
      2. If C1E promotion bit is enabled.
         a. C1  requests end up with C1E C-state.
         b. C1E requests end up with C1E C-state.
      
      Before SPR Xeon, the 'intel_idle' driver was disabling C1E promotion and was
      exposing C1 and C1E as independent C-states. But on SPR, C1 and C1E cannot be
      enabled at the same time.
      
      This patch adds both C1 and C1E states. However, C1E is marked as with the
      "CPUIDLE_FLAG_UNUSABLE" flag, which means that in won't be registered by
      default. The C1E promotion bit will be cleared, which means that by default
      only C1 and C6 will be registered on SPR.
      
      The next patch will add an option for enabling C1E and disabling C1 on SPR.
      Signed-off-by: default avatarArtem Bityutskiy <artem.bityutskiy@linux.intel.com>
      Signed-off-by: default avatarRafael J. Wysocki <rafael.j.wysocki@intel.com>
      9edf3c0f
  2. 03 Mar, 2022 2 commits
  3. 27 Feb, 2022 4 commits
  4. 26 Feb, 2022 22 commits
  5. 25 Feb, 2022 9 commits