- 31 Jan, 2023 5 commits
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Dmitry Baryshkov authored
The eDP device doesn't provide sound DAI. Drop corresponding property from the eDP node. Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230118031718.1714861-3-dmitry.baryshkov@linaro.org
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Melody Olvera authored
Add DTs for Qualcomm IDP platforms using the QDU1000 and QRU1000 SoCs. Signed-off-by:
Melody Olvera <quic_molvera@quicinc.com> Signed-off-by:
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Melody Olvera authored
Add the base DTSI files for QDU1000 and QRU1000 SoCs, including base descriptions of CPUs, GCC, RPMHCC, QUP, TLMM, and interrupt-controller to boot to shell with console on these SoCs. Signed-off-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
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Bjorn Andersson authored
Merge DT binding in order to get GCC clock defines.
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Bjorn Andersson authored
Merge branch 'icc-qdu1000-immutable' of https://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc into HEAD Merge DT binding to gain interconnect defines.
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- 26 Jan, 2023 7 commits
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Konrad Dybcio authored
Somehow DSI1 was not hooked up to MDP resulting in it not working. Fix it. Fixes: d4a44105 ("arm64: dts: qcom: sm8350: Add display system nodes") Signed-off-by:
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Konrad Dybcio authored
Add the mdss_ prefix to DSIn labels, so that the hardware blocks can be organized near each other while retaining the alphabetical order in device DTs when referencing by label. Signed-off-by:
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Konrad Dybcio authored
As downstream indicates, DSI PLL is actually 0x27c and not 0x260- wide. Fix that to reserve the correct registers. Fixes: d4a44105 ("arm64: dts: qcom: sm8350: Add display system nodes") Signed-off-by:
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Konrad Dybcio authored
The compatibles were wrong, resulting in the driver not probing. Fix that. Fixes: d4a44105 ("arm64: dts: qcom: sm8350: Add display system nodes") Signed-off-by:
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Konrad Dybcio authored
This was omitted but is necessary for DSI1 to function. Fix it. Fixes: d4a44105 ("arm64: dts: qcom: sm8350: Add display system nodes") Signed-off-by:
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Konrad Dybcio authored
The interrupt was wrong, likely copypasted from DSI0. Fix it. Fixes: d4a44105 ("arm64: dts: qcom: sm8350: Add display system nodes") Signed-off-by:
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Konrad Dybcio authored
Panels/DRM bridges definitely don't need 64bits of address space and are usually not 32-bit wide. Set address-cells to 1 and size-cells to 0. Signed-off-by:
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- 19 Jan, 2023 28 commits
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Sibi Sankar authored
Add a new carveout for modem metadata on SC7280 SoCs. Signed-off-by:
Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by:
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Sibi Sankar authored
Add a new carveout for modem metadata on SC7180 SoCs. Signed-off-by:
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Sibi Sankar authored
Add a new carveout for modem metadata on SDM845 SoCs. Tested-by:
Amit Pundir <amit.pundir@linaro.org> Signed-off-by:
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Sibi Sankar authored
Add a new carveout for modem metadata on MSM8998 SoCs. Signed-off-by:
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Sibi Sankar authored
Add a new carveout for modem metadata on MSM8996 SoCs. Signed-off-by:
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Robert Marko authored
Current PCIe QMP PHY output name were changed in ("arm64: dts: qcom: Fix IPQ8074 PCIe PHY nodes") however it did not account for the fact that GCC driver is relying on the old names to match them as they are being used as the parent for the gcc_pcie0_pipe_clk and gcc_pcie1_pipe_clk. This broke parenting as GCC could not find the parent clock, so fix it by changing to the names that driver is expecting. Fixes: 942bcd33 ("arm64: dts: qcom: Fix IPQ8074 PCIe PHY nodes") Signed-off-by:Robert Marko <robimarko@gmail.com> Signed-off-by:
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Robert Marko authored
IPQ8074 comes in 2 silicon versions: * v1 with 2x Gen2 PCIe ports and QMP PHY-s * v2 with 1x Gen3 and 1x Gen2 PCIe ports and QMP PHY-s v2 is the final and production version that is actually supported by the kernel, however it looks like PCIe related nodes were added for the v1 SoC. Finish the PCIe fixup by using the correct compatible, adding missing ATU register space, declaring max-link-speed, use correct ranges, add missing clocks and resets. Fixes: 33057e16 ("ARM: dts: ipq8074: Add pcie nodes") Signed-off-by:
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Robert Marko authored
Add the generic 'max-link-speed' property to describe the Gen2 PCIe link generation limit. This allows the generic DWC code to configure the link speed correctly. Signed-off-by:
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Robert Marko authored
Current ranges property set in Gen2 PCIe node is incorrect, replace it with the downstream 5.4 QCA kernel value. Fixes: 33057e16 ("ARM: dts: ipq8074: Add pcie nodes") Signed-off-by:
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Robert Marko authored
IPQ8074 comes in 2 silicon versions: * v1 with 2x Gen2 PCIe ports and QMP PHY-s * v2 with 1x Gen3 and 1x Gen2 PCIe ports and QMP PHY-s v2 is the final and production version that is actually supported by the kernel, however it looks like PCIe related nodes were added for the v1 SoC. Now that we have Gen3 QMP PHY support, we can start fixing the PCIe support by fixing the Gen3 QMP PHY node first. Change the compatible to the Gen3 QMP PHY, correct the register space start and size, add the missing misc PCS register space. Fixes: 33057e16 ("ARM: dts: ipq8074: Add pcie nodes") Signed-off-by:
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Robert Marko authored
Serdes register space sizes are incorrect, update them to match the actual sizes from downstream QCA 5.4 kernel. Fixes: 942bcd33 ("arm64: dts: qcom: Fix IPQ8074 PCIe PHY nodes") Signed-off-by:
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Krzysztof Kozlowski authored
Geni I2C Controller node does not allow a "label" property and Linux driver does not parse it: sdm845-db845c.dtb: i2c@a8c000: Unevaluated properties are not allowed ('label' was unexpected) Signed-off-by:Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
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Dmitry Baryshkov authored
In some cases the driver might need using GPLL0 to drive CPU clocks. Bring it in through the sys_apcs_aux clock. Signed-off-by:
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Melody Olvera authored
Add device tree bindings for global clock controller on QDU1000 and QRU1000 SoCs. Signed-off-by:
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Manivannan Sadhasivam authored
The devicetree should specify both MSI implementations and the OS/driver should choose the one based on the platform requirements. Currently, Linux DWC driver will choose GIC-ITS over the internal MSI controller. Fixes: a11bbf6adef4 ("arm64: dts: qcom: sm8450: Use GIC-ITS for PCIe0 and PCIe1") Suggested-by:Rob Herring <robh@kernel.org> Signed-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by:
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Abel Vesa authored
Enable USB HC and PHYs nodes on SM8550 MTP board. Signed-off-by:
Abel Vesa <abel.vesa@linaro.org> Signed-off-by:
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Abel Vesa authored
Add USB host controller and PHY nodes. Signed-off-by:
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Krzysztof Kozlowski authored
Neither qcom,sm8250-lpass-tx-macro bindings nor the driver use "clock-frequency" and address/size cells properties. sm8250-mtp.dtb: txmacro@3220000: Unevaluated properties are not allowed ('clock-frequency', '#address-cells', '#size-cells' were unexpected) Signed-off-by: -
Krzysztof Kozlowski authored
Neither qcom,sm8250-lpass-wsa-macro bindings nor the driver use "clock-frequency" property. sm8250-hdk.dtb: codec@3240000: Unevaluated properties are not allowed ('clock-frequency' was unexpected) Signed-off-by: -
Krzysztof Kozlowski authored
Bindings expect OPP tables to start with "opp-table". Signed-off-by:
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Dmitry Baryshkov authored
Follow the schema change and rename mdp nodes to generic name 'display-controller'. Signed-off-by:
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Dmitry Baryshkov authored
Follow the schema change and rename mdss nodes to generic name 'display-subsystem'. Signed-off-by:
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Dmitry Baryshkov authored
Add SoC-specific compat string to the MDP5 device nodes to ease distinguishing between various platforms. Signed-off-by:
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Robert Marko authored
It seems that clock-output-names for the USB3 QMP PHY-s where set without actually checking what is the GCC clock driver expecting, so clock core could never actually find the parents for usb0_pipe_clk_src and usb1_pipe_clk_src clocks in the GCC driver. So, correct the names to be what the driver expects so that parenting works. Before: gcc_usb0_pipe_clk_src 0 0 0 125000000 0 0 50000 Y gcc_usb1_pipe_clk_src 0 0 0 125000000 0 0 50000 Y After: usb3phy_0_cc_pipe_clk 1 1 0 125000000 0 0 50000 Y usb0_pipe_clk_src 1 1 0 125000000 0 0 50000 Y gcc_usb0_pipe_clk 1 1 0 125000000 0 0 50000 Y usb3phy_1_cc_pipe_clk 1 1 0 125000000 0 0 50000 Y usb1_pipe_clk_src 1 1 0 125000000 0 0 50000 Y gcc_usb1_pipe_clk 1 1 0 125000000 0 0 50000 Y Fixes: 5e09bc51 ("arm64: dts: ipq8074: enable USB support") Signed-off-by: -
Siddharth Manthan authored
Galaxy Tab A 8.0 is a tablet, very similar to Tab A 9.7 with major differences being the display and touchscreen. Add it's devicetree reusing a common dtsi from gt510. Signed-off-by:
Siddharth Manthan <siddharth.manthan@gmail.com> [Squashed multiple commits] Reviewed-by:
Nikita Travkin <nikita@trvn.ru> Signed-off-by:
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Jasper Korten authored
The Galaxy Tab A 9.7 (2015) is a Snapdragon 410 based tablet. This commit introduces basic support for the tablet including the following features: - SDHCI (internal and external storage) - USB Device Mode - UART - Regulators - WCNSS (WiFi/BT) - GPIO keys - Fuel gauge - Touchscreen - Accelerometer Part of the DT is split out into a common dtsi since the tablet shares majority of the design with another variant having a different screen size. Signed-off-by:
Jasper Korten <jja2000@gmail.com> Co-developed-by:
Siddharth Manthan <siddharth_manthan@outlook.com> Signed-off-by:
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Brian Masney authored
Add the necessary device tree node for qcom,prng-ee so we can use the hardware random number generator. This functionality was tested on a SA8540p automotive development board using kcapi-rng from libkcapi. Signed-off-by:
Brian Masney <bmasney@redhat.com> Reviewed-by:
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Brian Masney authored
Add aliases for i2c4 and i2c21 to the crd and x13s DTS files so that what's exposed to userspace doesn't change in the future if additional i2c buses are enabled on these platforms. Signed-off-by:
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