- 03 Aug, 2020 1 commit
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Thomas Gleixner authored
Merge tag 'irqchip-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core Pull irqchip updates from Marc Zyngier: - Add infrastructure to allow DT irqchip platform drivers to be built as modules - Allow qcom-pdc, mtk-cirq and mtk-sysirq to be built as module - Fix ACPI probing to avoid abusing function pointer casting - Allow bcm7120-l2 and brcmstb-l2 to be used as wake-up sources - Teach NXP's IMX INTMUX some power management - Allow stm32-exti to be used as a hierarchical irqchip - Let stm32-exti use the hw spinlock API in its full glory - A couple of GICv4.1 fixes - Tons of cleanups (mtk-sysirq, aic5, bcm7038-l1, imx-intmux, brcmstb-l2, ativic32, ti-sci-inta, lonsoon, MIPS GIC, GICv3)
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- 30 Jul, 2020 5 commits
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Huacai Chen authored
Loongson PCH PIC is a standard level triggered PIC, and it need to clear interrupt during unmask. Fixes: ef8c01eb ("irqchip: Add Loongson PCH PIC controller") Signed-off-by:
Huacai Chen <chenhc@lemote.com> Signed-off-by:
Marc Zyngier <maz@kernel.org> Tested-by:
Jiaxun Yang <jiaxun.yang@flygoat.com> Link: https://lore.kernel.org/r/1596099090-23516-6-git-send-email-chenhc@lemote.com
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Huacai Chen authored
The original version can only used by old Loongson-3 which only use 4 groups of HT vectors. Now Loongson-3A R4 can use 8 groups, so improve the driver to support all 8 groups. Fixes: 818e915f ("irqchip: Add Loongson HyperTransport Vector support") Signed-off-by:
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Huacai Chen authored
In gc->mask_cache bits, 1 means enabled and 0 means disabled, but in the loongson-liointc driver mask_cache is misused by reverting its meaning. This patch fix the bug and update the comments as well. Fixes: dbb15226 ("irqchip: Add driver for Loongson I/O Local Interrupt Controller") Signed-off-by:
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Huacai Chen authored
Loongson HTVEC support 8 parents interrupts in maximum, so update the maxItems description. Signed-off-by:
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Wei Yongjun authored
Gcc report warning as follows: drivers/irqchip/irq-imx-intmux.c:316:29: warning: variable 'irqchip_data' set but not used [-Wunused-but-set-variable] 316 | struct intmux_irqchip_data irqchip_data; | ^~~~~~~~~~~~ irqdata regs is stored to this variable on the stack in imx_intmux_runtime_suspend(), which means a nop. this commit fix to save regs to the right place. Fixes: bb403111 ("irqchip/imx-intmux: Implement intmux runtime power management") Reported-by:Hulk Robot <hulkci@huawei.com> Signed-off-by:
Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by:
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- 27 Jul, 2020 19 commits
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Joakim Zhang authored
When the system is suspended, we can explicitly disable clock to save power. To achieve this, we need save registers' state since it could be lost after power off. Implement power management which will: - Turn the clock off after probing - Disable clock and save registers' state on system suspend, as well as enable clock and restore registers' state on resume - Rely on the Power Domain framework to shutdown the intmux power domain Without CONFIG_PM, the clock is always on after probe stage. Signed-off-by:
Joakim Zhang <qiangqing.zhang@nxp.com> [maz: revamped commit message] Signed-off-by:
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Zenghui Yu authored
Booting the latest kernel with DEBUG_ATOMIC_SLEEP=y on a GICv4.1 enabled box, I get the following kernel splat: [ 0.053766] BUG: sleeping function called from invalid context at mm/slab.h:567 [ 0.053767] in_atomic(): 1, irqs_disabled(): 128, non_block: 0, pid: 0, name: swapper/1 [ 0.053769] CPU: 1 PID: 0 Comm: swapper/1 Not tainted 5.8.0-rc3+ #23 [ 0.053770] Call trace: [ 0.053774] dump_backtrace+0x0/0x218 [ 0.053775] show_stack+0x2c/0x38 [ 0.053777] dump_stack+0xc4/0x10c [ 0.053779] ___might_sleep+0xfc/0x140 [ 0.053780] __might_sleep+0x58/0x90 [ 0.053782] slab_pre_alloc_hook+0x7c/0x90 [ 0.053783] kmem_cache_alloc_trace+0x60/0x2f0 [ 0.053785] its_cpu_init+0x6f4/0xe40 [ 0.053786] gic_starting_cpu+0x24/0x38 [ 0.053788] cpuhp_invoke_callback+0xa0/0x710 [ 0.053789] notify_cpu_starting+0xcc/0xd8 [ 0.053790] secondary_start_kernel+0x148/0x200 # ./scripts/faddr2line vmlinux its_cpu_init+0x6f4/0xe40 its_cpu_init+0x6f4/0xe40: allocate_vpe_l1_table at drivers/irqchip/irq-gic-v3-its.c:2818 (inlined by) its_cpu_init_lpis at drivers/irqchip/irq-gic-v3-its.c:3138 (inlined by) its_cpu_init at drivers/irqchip/irq-gic-v3-its.c:5166 It turned out that we're allocating memory using GFP_KERNEL (may sleep) within the CPU hotplug notifier, which is indeed an atomic context. Bad thing may happen if we're playing on a system with more than a single CommonLPIAff group. Avoid it by turning this into an atomic allocation. Fixes: 5e516846 ("irqchip/gic-v4.1: VPE table (aka GICR_VPROPBASER) allocation") Signed-off-by:
Zenghui Yu <yuzenghui@huawei.com> Signed-off-by:
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Marc Zyngier authored
The newly introduced IRQCHIP_PLATFORM_DRIVER_* macros expand into module-related macros, but do so without including module.h. Depending on the driver and/or architecture, this happens to work, or not. Unconditionnaly include linux/module.h to sort it out. Fixes: f3b5e608ed6d ("irqchip: Add IRQCHIP_PLATFORM_DRIVER_BEGIN/END and IRQCHIP_MATCH helper macros") Reported-by:kernel test robot <lkp@intel.com> Cc: Saravana Kannan <saravanak@google.com> Signed-off-by:
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Alexandre Torgue authored
EXTI lines are mainly used to wake-up system from CStop low power mode. Currently, if a device wants to use a EXTI (direct) line as wakeup line, it has to declare 2 interrupts: - one for EXTI used to wake-up system (with dedicated_wake_irq api). - one for GIC used to get the wake up reason inside the concerned IP. This split is not really needed as each EXTI line is actually "linked " to a GIC. So to avoid this useless double interrupt management in each wake-up driver, this patch lets the STM32 EXTI driver abstract it by mapping each EXTI line to his corresponding GIC. Signed-off-by:
Alexandre Torgue <alexandre.torgue@st.com> Signed-off-by:
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Saravana Kannan authored
This driver can work as a platform driver. So covert it to a platform driver. Signed-off-by:
Saravana Kannan <saravanak@google.com> Signed-off-by:
Hanks Chen <hanks.chen@mediatek.com> Link: https://lore.kernel.org/r/20200718000637.3632841-5-saravanak@google.com
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Saravana Kannan authored
This driver can work as a platform driver. So covert it to a platform driver. Signed-off-by:
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Saravana Kannan authored
Switch the driver to use the helper macros. In addition to reducing the number of lines, this also adds module unload protection (if the driver is compiled as a module) by switching from module_platform_driver to builtin_platform_driver. Signed-off-by:
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Saravana Kannan authored
Compiling an irqchip driver as a platform driver needs to bunch of things to be done right: - Making sure the parent domain is initialized first - Making sure the device can't be unbound from sysfs - Disallowing module unload if it's built as a module - Finding the parent node - Etc. Instead of trying to make sure all future irqchip platform drivers get this right, provide boilerplate macros that take care of all of this. An example use would look something like this. Where acme_foo_init and acme_bar_init are similar to what would be passed to IRQCHIP_DECLARE. IRQCHIP_PLATFORM_DRIVER_BEGIN(acme_irq) IRQCHIP_MATCH("acme,foo", acme_foo_init) IRQCHIP_MATCH("acme,bar", acme_bar_init) IRQCHIP_PLATFORM_DRIVER_END(acme_irq) Signed-off-by: -
Randy Dunlap authored
Drop the repeated word "the" in a comment. Signed-off-by:
Randy Dunlap <rdunlap@infradead.org> Signed-off-by:
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Zenghui Yu authored
The GICv4.1 spec tells us that it's CONSTRAINED UNPREDICTABLE to issue a register-based invalidation operation for a vPEID not mapped to that RD, or another RD within the same CommonLPIAff group. To follow this rule, commit f3a05921 ("irqchip/gic-v4.1: Ensure mutual exclusion between vPE affinity change and RD access") tried to address the race between the RD accesses and the vPE affinity change, but somehow forgot to take GICR_INVALLR into account. Let's take the vpe_lock before evaluating vpe->col_idx to fix it. Fixes: f3a05921 ("irqchip/gic-v4.1: Ensure mutual exclusion between vPE affinity change and RD access") Signed-off-by:
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Florian Fainelli authored
cpu_logical_map is only defined for CONFIG_SMP builds, when we are in an UP configuration, the boot CPU is 0. Fixes: 6468fc18 ("irqchip/irq-bcm7038-l1: Add PM support") Reported-by:
Florian Fainelli <f.fainelli@gmail.com> Signed-off-by:
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Zenghui Yu authored
[maz: The GICv3 spec has evolved quite a bit since the draft the Linux driver was written against, and some register definitions are simply gone] As per the GICv3 specification, GIC{D,R}_SEIR are not assigned and the locations (0x0068) are actually Reserved. GICR_MOV{LPI,ALL}R are two IMP DEF registers and might be defined by some specific micro-architecture. As they're not used anywhere in the kernel, just drop all of them. Signed-off-by: -
John Stultz authored
Allows qcom-pdc driver to be loaded as a permanent module Also, due to the fact that IRQCHIP_DECLARE becomes a no-op when building as a module, we have to replace it with platform driver hooks explicitly. Thanks to Saravana for his help on pointing out the IRQCHIP_DECLARE issue and guidance on a solution. Signed-off-by:
John Stultz <john.stultz@linaro.org> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org> Cc: Andy Gross <agross@kernel.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Joerg Roedel <joro@8bytes.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <maz@kernel.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Maulik Shah <mkshah@codeaurora.org> Cc: Lina Iyer <ilina@codeaurora.org> Cc: Saravana Kannan <saravanak@google.com> Cc: Todd Kjos <tkjos@google.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: linux-arm-msm@vger.kernel.org Cc: iommu@lists.linux-foundation.org Cc: linux-gpio@vger.kernel.org Link: https://lore.kernel.org/r/20200710231824.60699-4-john.stultz@linaro.org
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John Stultz authored
Add EXPORT_SYMBOL_GPL entries for irq_chip_retrigger_hierarchy() and irq_chip_set_vcpu_affinity_parent() so that we can allow drivers like the qcom-pdc driver to be loadable as a module. Signed-off-by:
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John Stultz authored
Add export for irq_domain_update_bus_token() so that we can allow drivers like the qcom-pdc driver to be loadable as a module. Signed-off-by:
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Wei Yongjun authored
The sparse tool complains as follows: drivers/irqchip/irq-mips-gic.c:49:1: warning: symbol '__pcpu_scope_pcpu_masks' was not declared. Should it be static? drivers/irqchip/irq-mips-gic.c:620:6: warning: symbol 'gic_ipi_domain_free' was not declared. Should it be static? drivers/irqchip/irq-mips-gic.c:634:5: warning: symbol 'gic_ipi_domain_match' was not declared. Should it be static? Those symbols are not used outside of irq-mips-gic.c, so marks them static. Reported-by:
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Zenghui Yu authored
The is_fwnode_irqchip() helper will check if the fwnode_handle is empty. There is no need to perform a redundant check outside of it. Signed-off-by:
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Masahiro Yamada authored
This is passed to irq_domain_add_linear(), which accepts a pointer to a const structure. Signed-off-by:
Masahiro Yamada <masahiroy@kernel.org> Signed-off-by:
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Fabien Dessenne authored
Now that the hwspin_lock_timeout_in_atomic() API is available use it. Signed-off-by:
Fabien Dessenne <fabien.dessenne@st.com> Signed-off-by:
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- 17 Jul, 2020 14 commits
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Tiezhu Yang authored
In the function liointc_set_type(), we need to call the function irq_gc_unlock_irqrestore() before returning. Fixes: dbb15226 ("irqchip: Add driver for Loongson I/O Local Interrupt Controller") Reported-by:
Jianmin Lv <lvjianmin@loongson.cn> Signed-off-by:
Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by:
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Tiezhu Yang authored
irq_domain_alloc_irqs_parent() returns 0 on success and non-zero value on failure, it is redudant to check its non-zero return value and then return it, so just remove the variable "ret" and return directly in the function pch_msi_parent_domain_alloc(). Signed-off-by:
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Tiezhu Yang authored
Check the return value of irq_domain_translate_twocell() due to it may returns -EINVAL if failed and use variable fwspec for it, and then use a new variable parent_fwspec which is proper for irq_domain_alloc_irqs_parent(). Fixes: ef8c01eb ("irqchip: Add Loongson PCH PIC controller") Signed-off-by:
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Tiezhu Yang authored
Check the return value of irq_domain_translate_onecell() due to it may returns -EINVAL if failed. Fixes: 818e915f ("irqchip: Add Loongson HyperTransport Vector support") Signed-off-by:
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Tiezhu Yang authored
In the function htvec_of_init(), system resource "parent_irq" was not released in an error case. Thus add a jump target for the completion of the desired exception handling. Fixes: 818e915f ("irqchip: Add Loongson HyperTransport Vector support") Signed-off-by:
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Tiezhu Yang authored
LOONGSON_HTPIC depends on MACH_LOONGSON64 and MACH_LOONGSON64 already selects I8259 in arch/mips/Kconfig, so no need to select I8259 again when config LOONGSON_HTPIC. Signed-off-by:
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Tiezhu Yang authored
In the function htpic_of_init(), when kzalloc htpic fails, it should return -ENOMEM directly, no need to execute "goto" to kfree. Signed-off-by:
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Florian Fainelli authored
We need to have a definition for cpu_logical_map[] which on ARM platforms is provided by asm/smp_plat.h. This header is not automatically included from linux/smp.h and untangling it is a bit difficult. Signed-off-by:
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Florian Fainelli authored
The UPG_AUX_AON_INTR2 Level 2 interrupt controller node is defined with the "brcm,upg-aux-aon-l2-intc" compatible string in Device Tree and behaves as an edge triggered standard Broadcom STB L2 interrupt controller. Signed-off-by:
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Florian Fainelli authored
Define the compatible string brcm,upg-aux-aon-l2-intc which is used by the Broadcom STB UPG auxiliary always-on interrupt controller. Signed-off-by:
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Kamal Dasu authored
The HIF_SPI_INTR2 Level 2 interrupt controller node is defined with the "brcm,hif-spi-l2-intc" compatible string in Device Tree and behaves as an edge triggered standard Broadcom STB L2 interrupt controller. Signed-off-by:
Kamal Dasu <kdasu.kdev@gmail.com> Signed-off-by:
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Florian Fainelli authored
Add documentation for the brcm,hif-spi-l2-intc compatible string to the brcm,l2-intc.txt binding document. Signed-off-by:
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Justin Chen authored
Utilize the Broadcom interrupt controller standard property "brcm,irq-can-wake" to flag whether this particular interrupt controller instance is wake-up capable. Since we do not know what type of parent interrupt controller we are interfaced with, ensure that enable_irq_wake() is called early on. Signed-off-by:
Justin Chen <justinpopo6@gmail.com> Signed-off-by:
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Justin Chen authored
Utilize the Broadcom interrupt controller standard property "brcm,irq-can-wake" to flag whether this particular interrupt controller instance is wake-up capable. Since we do not know what type of parent interrupt controller we are interfaced with, ensure that enable_irq_wake() is called early on. Signed-off-by:
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- 04 Jul, 2020 1 commit
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Valentin Schneider authored
That was put in place for sparc64, and blackfin also used it for some time; sparc64 no longer uses those, and blackfin is dead. As there are no more users, remove preflow handlers. Signed-off-by:
Valentin Schneider <valentin.schneider@arm.com> Signed-off-by:
Thomas Gleixner <tglx@linutronix.de> Link: https://lkml.kernel.org/r/20200703155645.29703-3-valentin.schneider@arm.com
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