- 22 May, 2014 9 commits
-
-
Antoine Tenart authored
The Marvell Berlin boards have a group based pinmuxing mechanism. This adds the core driver support. We actually do not need any information about the pins here and only have the definition of the groups. Let's take the example of the uart0 pinmuxing on the BG2Q. Balls BK4 and BH6 are muxed to respectively UART0 RX and TX if the group GSM12 is set to mode 0: Group Modes Offset Base Offset LSB Bit Width GSM12 3 sm_base 0x40 0x10 0x2 Ball Group Mode 0 Mode 1 Mode 2 BK4 GSM12 UART0_RX IrDA0_RX GPIO9 BH6 GSM12 UART0_TX IrDA0_TX GPIO10 So in order to configure BK4 -> UART0_TX and BH6 -> UART0_RX, we need to set (sm_base + 0x40 + 0x10) &= ff3fffff. As pin control registers are part of either chip control or system control registers, that deal with a bunch of other functions we rely on a regmap instead of exclusively remapping any resources. Signed-off-by:
Antoine Tenart <antoine.tenart@free-electrons.com> Acked-by:
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
-
Mika Westerberg authored
In case of resolving power management or similar issues it might be useful to have these properties included in the debugfs output. Signed-off-by:
Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by:
Mathias Nyman <mathias.nyman@linux.intel.com> Signed-off-by:
-
Jin Yao authored
If chip->to_irq is NULL ACPI GPIO helpers don't register GPIO event handlers thus preventing any ACPI GPIO triggered events. Solve this by calling gpiochip_add() after we have set up drivers chip->to_irq hook. Signed-off-by:
Jin Yao <yao.jin@intel.com> Signed-off-by:
-
Jin Yao authored
Now that the x86 dynamic IRQ allocation problem has been resolved with commmit 62a08ae2 (genirq: x86: Ensure that dynamic irq allocation does not conflict), we can add back Baytrail-T ACPI ID to the pinctrl driver. This makes the driver to work on Asus T100 where it is needed for several things like ACPI GPIO events and SD card detection. References: https://bugzilla.kernel.org/show_bug.cgi?id=68291Acked-by:
Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by:
-
Magnus Damm authored
Add #ifdefs to allow r8a73a4 Multiplatform build. Needed to enable r8a73a4 Multiplatform support. Signed-off-by:
Magnus Damm <damm+renesas@opensource.se> Signed-off-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by:
-
Magnus Damm authored
Add #ifdefs to allow sh73a0 Multiplatform build. Needed to enable sh73a0 Multiplatform support. Signed-off-by:
-
Magnus Damm authored
Add #ifdefs to allow r8a7740 Multiplatform build. Needed to enable r8a7740 Multiplatform support. Signed-off-by:
-
Laurent Pinchart authored
In the multiplatform kernel case the IRQs associated with the PFC GPIOs are specified through DT. The pinmux_irq irq field is thus ignored by the code, and doesn't need to be set. This will allow removing the mach/irq.h include from pfc-*.c files that was required for the irq_pin() macro used to initialize the irq field. Signed-off-by:
-
Maxime Ripard authored
Enable the freshly introduced Kconfig options whenever their matching architecture is enabled. Since the Kconfig symbols for these machines are going through a different tree, keep PINCTRL_SUNXI around for the moment to avoid breaking the defconfig. It should be removed eventually. Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by:
-
- 09 May, 2014 8 commits
-
-
Heiko Stübner authored
Introduce the syscons for grf and pmu and deprecate the previous register areas. Signed-off-by:
Heiko Stuebner <heiko@sntech.de> Tested-by:
Max Schwarz <max.schwarz@online.de> Signed-off-by:
-
Heiko Stübner authored
This allows the basic registers of the general register files to be supplied by a syscon instead of being mapped locally. The GRF registers contain a lot more than pinctrl functions like dma, usb-phy and general soc control and status registers, intermixed with the iomux, pull and drive-strength registers. Signed-off-by:
-
Heiko Stübner authored
When the pmu registers are supplied through a syscon regmap we do not need to map the registers ourself. Signed-off-by:
-
Heiko Stübner authored
Currently the pmu registers containing pin pull settings on the rk3188 are mapped locally when bank0 is instantiated. Add an alternative that can resolve the pmu from a syscon phandle. Signed-off-by:
-
Heiko Stübner authored
Convert rockchip_get_bank_data to use the struct rockchip_pinctrl because later on we need to check a value from it when registering the gpio banks. Signed-off-by:
-
Heiko Stübner authored
This allows us to use syscons in the future. Signed-off-by:
-
Heiko Stübner authored
Deprecate secondary register area for rk3188 pulls. Instead use big enough initial mapping of grf registers to catch all. The now deprecated register is still supported though. Signed-off-by:
-
https://github.com/mripard/linuxLinus Walleij authored
Pinctrl cleanup and reworks for 3.16 This serie of patch: - Moves the Allwinner pinctrl driver to a folder of its own - removes the sunxi-pinctrl-pins header, and split the driver into a core one, with all the logic, and smaller drivers, one for each SoC, that declare the pins, and will provide to the core the set of pins. - And does a few cleanups here and there.
-
- 05 May, 2014 2 commits
-
-
Maxime Ripard authored
The way that reset is handled right now is that it is made optional for every pinctrl driver, while actually, it isn't used at all for the main pin controllers so far, and while it's mandatory for the A31's secondary pin controller. Move the reset functions out of the core and in the driver, where they can be made mandatory. Signed-off-by: -
Maxime Ripard authored
Add one Kconfig option for each driver. This will allow to better control which driver is enabled, instead of having either all or nothing. Signed-off-by:
-
- 04 May, 2014 12 commits
-
-
Maxime Ripard authored
Move the pin description to a driver specific to be. This is the final step toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all the Allwinner SoCs in a single header, that would have in turn result in having these structures in the final binary as many times as the header was included. We can finally remove that header, and remove all the driver part of the pinctrl-sunxi core. Signed-off-by: -
Maxime Ripard authored
Move the pin description to a driver specific to be. This is one more step toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all the Allwinner SoCs in a single header, that would have in turn result in having these structures in the final binary as many times as the header was included. Signed-off-by: -
Maxime Ripard authored
Move the pin description to a driver specific to be. This is one more step toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all the Allwinner SoCs in a single header, that would have in turn result in having these structures in the final binary as many times as the header was included. Signed-off-by: -
Maxime Ripard authored
Move the pin description to a driver specific to be. This is one more step toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all the Allwinner SoCs in a single header, that would have in turn result in having these structures in the final binary as many times as the header was included. Signed-off-by: -
Maxime Ripard authored
Move the pin description to a driver specific to be. This is one more step toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all the Allwinner SoCs in a single header, that would have in turn result in having these structures in the final binary as many times as the header was included. Signed-off-by: -
Maxime Ripard authored
Move the pin description to a driver specific to be. This is one more step toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all the Allwinner SoCs in a single header, that would have in turn result in having these structures in the final binary as many times as the header was included. Signed-off-by: -
Maxime Ripard authored
This will allow to have multiple drivers using the same core code, and eventually, retire pinctrl-sunxi-pins.h Signed-off-by: -
Maxime Ripard authored
The previous code was calling of_iomap, which doesn't do any resource management, and doesn't call request_mem_region either. Use devm_ioremap_resource that do both. Signed-off-by: -
Maxime Ripard authored
We previously had an evergrowing (and exhaustive) list of the pins that could be used on any Allwinner SoCs. These defines were then used by each pinctrl driver to declare the list of functions for this pin. Since it's pretty much all boilerplate, we can remove it just by a single macro. Signed-off-by: -
Maxime Ripard authored
This will allow to create numerous files without crippling the main pinctrl directory. Signed-off-by: -
Maxime Ripard authored
The ranges and nranges were never used. Remove them. Signed-off-by: -
Maxime Ripard authored
The pins description structure were declared as const, but the of_device_id data magic was losing it silently. Make sure we have it on both sides. And now that we're using const, we can also remove the useless cast in probe. Signed-off-by:
-
- 02 May, 2014 1 commit
-
-
Andy Gross authored
Fix copy/paste error in pinctrl_pin_desc for pin 0. Signed-off-by:
Andy Gross <agross@codeaurora.org> Signed-off-by:
-
- 24 Apr, 2014 1 commit
-
-
Thomas Petazzoni authored
This commit extends the pinctrl mvebu logic with a new driver to cover Orion5x SoC. It supports the definitions for the 5181l, 5182 and 5281 variants of Orion5x, which are the three ones supported by the old style MPP code in arch/arm/mach-orion5x/. Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by:
-
- 23 Apr, 2014 7 commits
-
-
Heiko Stübner authored
In some cases it is nice to be able to simply control a gpio output via the PIN_CONFIG_OUTPUT option without having a driver control it. Thus add support for it to the rockchip pinctrl driver. Signed-off-by:
-
Heiko Stübner authored
Till now pinconf_get only set the argument value into the config parameter effectively removing the actual config param value. As other pinctrl drivers do, it might be nicer to keep the config param intact. Therefore construct a real pinconfig value from param and arg in pinconf_get Signed-off-by:
-
Linus Walleij authored
This switches the SiRF pinctrl driver over to using the gpiolib irqchip helpers simplifying some of the code. Signed-off-by:
Barry Song <Baohua.Song@csr.com> Signed-off-by:
-
Barry Song authored
all gpio banks are in one chip, that makes software clean in mapping irq and gpio. Signed-off-by:
-
Linus Walleij authored
The sirfsoc_irqchip_to_bank() is obviously misnamed, as it is not converting an irqchip to a bank but converts a gpiochip to a bank so rename it sirfsoc_gpiochip_to_bank(). Acked-by:
-
Andy Gross authored
Define a new binding for the Qualcomm TLMMv2 based pin controller inside the IPQ8064. Signed-off-by:
Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by:
-
Andy Gross authored
This adds pinctrl definitions for the GPIO pins of the TLMM v2 block in the Qualcomm IPQ8064 platform. Signed-off-by:
-
