- 13 Sep, 2022 40 commits
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Aric Cyr authored
This version brings along following fixes: *Fixed register definitions for DCN32/321 *Adding log for spread_spectrum_info *Reverted DSC programming sequence change *Correct I2C register offset *Updated DCN30 header files, viewport position for phantom pipes *Enable dlg and vba compilation for dcn314 Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Acked-by:
Pavle Kotarac <Pavle.Kotarac@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Aurabindo Pillai authored
[Why & How] Fix the instatiation sequence for MPC registers and add a few other missing register definitions that were ommited erroneously when copying them over to enable runtime initialization of reigster offsets for DCN32/321 Tested-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
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Alvin Lee authored
Refactor calculation to remove floating point operations from dmub_srv. To ensure that 32-bit compilation works well, we use the div64 family of macros to do integer division for SubVP-related timing parameters. Cc: Maíra Canal <mairacanal@riseup.net> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Isabella Basso <isabbasso@riseup.net> Cc: Magali Lemes <magalilemes00@gmail.com> Tested-by:
Samson Tam <Samson.Tam@amd.com> Acked-by:
Tom Chung <chiahsuan.chung@amd.com> Signed-off-by:
Alvin Lee <alvin.lee2@amd.com> Co-developed-by:
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JeromeHong authored
[why] Call commit_minimal_transition_state wrongly in case of surface_count equal to 0. [how] Add a condition to filter case of surface_count equal to 0. Tested-by:
JeromeHong <jerome.hong@amd.com> Signed-off-by:
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Aric Cyr authored
[why] Do not need to spend time reprogramming DRR if there were no updates to the parameters. [how] Compare the current stream state to the requested one to determine if an update is required. In amdgpu_dm the timing_changed flag is set but never used so can remove it. Similarly, the stream update for VRR is done after dc_commit and should not update its adjust field until after the update is completed. The adjust field is managed by dc_stream_adjust_vmin_vmax and should not be manually updated in amdgpu_dm. Tested-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Leo Chen authored
[Why & How] Enable logging for spread_spectrum_percentage in spread_spectrum_info to facilitate debugging for audio compliance issues Tested-by:
Leo Chen <SanChuan.Chen@amd.com> Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
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Yao Wang1 authored
[Why] For HDR mode, we get total 512 tf_point and after switching to SDR mode we actually get 400 tf_point and the rest of points(401~512) still use dirty value from HDR mode. We should limit the rest of the points to max value. [How] Limit the value when coordinates_x.x > 1, just like what we do in translate_from_linear_space for other re-gamma build paths. Tested-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by:
Yao Wang1 <Yao.Wang1@amd.com> Signed-off-by:
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Aurabindo Pillai authored
[Why&How] Kernel does not have a means to tell the userspace to use software cursor. Due to lack of this functionality, reducing the max cursor size is the only way to ensure that power savings of Subview port feature is utilized for asics that support it. The workaround could be removed after cursor caching is fixed while a subviewport config is active. Tested-by:
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Lee, Alvin authored
[Description] Regkey option for forcing num ways for subvp for debug purposes Tested-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Alvin Lee authored
[Description] In some cases the viewport position of the main pipes can change without triggering a full update. In this case the subvp phantom viewports must be updated accordingly. Tested-by:
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Taimur Hassan authored
[Why & How] When calculating cursor size for MALL allocation, the cursor width should be the actual width rounded up to 64 alignment. Additionally, the bit depth should vary depending on color format. Tested-by:
Taimur Hassan <Syed.Hassan@amd.com> Signed-off-by:
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Duncan Ma authored
[Why] The interpretation of the number of memory channels differ by memory type, and this affects channel width for the DML input. [How] Set dram channel width according to memory type for dcn314. Tested-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Reviewed-by:
Duncan Ma <duncan.ma@amd.com> Signed-off-by:
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Nicholas Kazlauskas authored
[Why] HW can support the display swizzle modes for video, and those are preferable over standard or linear for decode use. [How] Remove the check for DCN314. Tested-by:
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Nicholas Kazlauskas authored
[Why & How] Add support for the DML314 functions and hook up DCN314 to use them. This has some necessary additions for calculating Max VSTARTUP for future features, but there's also some changes that we have to make for pixel format/swizzle support. That will come in a following patch to make this transition easier to bisect. Tested-by:
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Rodrigo Siqueira authored
We were not using the VBA and DLG files for DCN314, but the next sequence of changes for DCN314 will require those files. This commit adds the necessary files to the Makefile. Cc: Roman Li <roman.li@amd.com> Tested-by:
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Rodrigo Siqueira authored
We have some compilation errors in some DML files from DCN314 that we never noticed because we were not compiling some of the DML files. This commit fixes those syntax errors before we enable the compilation. Cc: Roman Li <roman.li@amd.com> Tested-by:
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Aric Cyr authored
[why] Incorrectly using MicroTileWidth instead of MacroTileWidth for calculations. [how] Remove all unused references to MicroTile and change them to MacroTile. Tested-by:
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Leo Chen authored
[Why & How] DIG_FIFO_READ_START_LEVEL should only be set to default value (7) by software. Removed all instances of resetting the register to 0 Tested-by:
Leo Chen <sancchen@amd.com> Signed-off-by:
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Alvin Lee authored
[Description] Leverage SW cursor fall back for SubVP when the cursor is too big. We want to take advantage of being able to fallback to SW cursor when possible because it's not worth it to disable MCLK switching because the cursor is slightly too big. Tested-by:
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JinZe.Xu authored
[Why] link type is not assigned before check dpia_mst_dsc_always_on conditions. Tested-by:
Wenjing Liu <Wenjing.Liu@amd.com> Acked-by:
JinZe.Xu <JinZe.Xu@amd.com> Signed-off-by:
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Nagulendran, Iswara authored
[HOW&WHY] Revert a previous commit by moving DSC programming back to before link enablement. Tested-by:
Jayendran Ramani <Jayendran.Ramani@amd.com> Acked-by:
Nagulendran, Iswara <Iswara.Nagulendran@amd.com> Signed-off-by:
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Alvin Lee authored
[Description] Update MBLK calculation according to hardware doc. For DCC case we were not allocation enough MALL due to an inaccurate MBLK calculation. Tested-by:
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Aurabindo Pillai authored
This reverts commit a4f1b042 since returning false in case of SubVP results in no cursor being visible on desktop as there is no sw cursor fallback path on all platforms. Tested-by:
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Chris Park authored
[Why] I2C register name starts with 1, unlike other registers that start with 0. This creates a problem with the new register macro refactoring when I2C HW objects are created in an array. [How] Correct I2C register offset by making a new macro to account for array offset. Tested-by:
Chris Park <chris.park@amd.com> Signed-off-by:
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Aric Cyr authored
[why] Conditionals in the DML basic math functions significantly impact mode enumeration. [how] Remove conditionals for floor/ceil operations which are used frequently in DML and add an assertion for invalid callers using zero granuality. Fix existing callers that rely on 0 granularity. Tested-by:
Nevenko Stupar <Nevenko.Stupar@amd.com> Acked-by:
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Candice Li authored
No need to reset error status since only umc ras supported on psp v13_0_0. Signed-off-by:
Candice Li <candice.li@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Candice Li authored
Set correct EEPROM I2C address for smu v13_0_0. Signed-off-by:
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John Clements authored
copy ras driver to psp if present Signed-off-by:
John Clements <john.clements@amd.com> Reviewed-by:
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Alex Deucher authored
Was missing before and would have resulted in a write to a non-existant register. Normally APUs don't use HDP, but other asics could use this code and APUs do use the HDP when used in passthrough. Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
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Jingyu Wang authored
Remove "default n" options. If the "default" line is removed, it defaults to 'n'. Signed-off-by:
Jingyu Wang <jingyuwang_vip@163.com> Signed-off-by:
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Jilin Yuan authored
Delete the redundant word 'in'. Signed-off-by:
Jilin Yuan <yuanjilin@cdjrlc.com> Signed-off-by:
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Jingyu Wang authored
Fix everything checkpatch.pl complained about in amdgpu_amdkfd_gpuvm.c Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Jingyu Wang authored
Fix everything checkpatch.pl complained about in amdgpu_amdkfd.c Signed-off-by:
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Jingyu Wang authored
This is a patch to the amdgpu_sync.c file that fixes some warnings found by the checkpatch.pl tool Signed-off-by:
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Jingyu Wang authored
Fix everything checkpatch.pl complained about in amdgpu_acpi.c Signed-off-by:
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zhang songyi authored
Return the sdma_v6_0_start() directly instead of storing it in another redundant variable. Reported-by:
Zeal Robot <zealci@zte.com.cn> Signed-off-by:
zhang songyi <zhang.songyi@zte.com.cn> Signed-off-by:
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ye xingchen authored
Return the value radeon_drm_ioctl() directly instead of storing it in another redundant variable. Reported-by:
ye xingchen <ye.xingchen@zte.com.cn> Signed-off-by:
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ye xingchen authored
Return the value ci_load_smc_ucode() directly instead of storing it in another redundant variable. Reported-by:
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Yang Li authored
Conditional statements have no effect to next process.So remove it. Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2028Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Signed-off-by:
Yang Li <yang.lee@linux.alibaba.com> Signed-off-by:
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Yang Li authored
The result of relational operation is Boolean, and the question mark expression is redundant. Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2027Reported-by:
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