- 19 Feb, 2018 40 commits
-
-
Charlene Liu authored
Signed-off-by:
Charlene Liu <charlene.liu@amd.com> Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
-
Geling Li authored
Signed-off-by:
Geling Li <geling.li@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
-
Krunoslav Kovac authored
Signed-off-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by:
-
Tony Cheng authored
Signed-off-by:
-
Charlene Liu authored
Signed-off-by:
-
Dmytro Laktyushkin authored
Directly editing pipe config outside of formula is error prone and results in higher clocks being used when splitting. For this reason we reverted to using bounding box hacking to split. Since sometimes this erroneusly results in higher dpm being required we unhack the bounding box and recalculate to allow dpm0 is possible. Side effect is we will lose some stutter efficiency in non dpm0 cases. This is not a big concern since increased stutter efficiency saves an order of magnitude less power than lower dpm. Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
-
Charlene Liu authored
Signed-off-by:
-
Arun Pandey authored
Signed-off-by:
Arun Pandey <Arun.Pandey@amd.com> Reviewed-by:
-
Charlene Liu authored
Signed-off-by:
-
Yongqiang Sun authored
Use tg count in resource pool for further reference. Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
-
SivapiriyanKumarasamy authored
Lock top_pipe when doing update plane addr for split pipe freesync case Signed-off-by:
SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com> Reviewed-by:
-
Harry Wentland authored
There's no good place in DC to cover all place where stream signal should be updated. update_stream_signal depends on timing which comes from DM. Signed-off-by:
-
Leo (Sunpeng) Li authored
If crc is disabled, early return when getting crc's. That way, we avoid reading extra registers within the pflip high irq. Signed-off-by:
Leo (Sunpeng) Li <sunpeng.li@amd.com> Reviewed-by:
-
Yongqiang Sun authored
Signed-off-by:
-
Ken Chalmers authored
Signed-off-by:
Ken Chalmers <ken.chalmers@amd.com> Signed-off-by:
-
Duke Du authored
Signed-off-by:
Duke Du <Duke.Du@amd.com> Signed-off-by:
-
Harry Wentland authored
We're currently not using this. v2: More files and includes to remove. Signed-off-by:
-
Alex Deucher authored
The IP soft reset interface is for per IP reset but it was being abused for adapter reset on soc15 asics. Adjust the interface to make it explicit. Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
-
Alex Deucher authored
This way we can make all of the IP specific functions static, and we only need a single entry point into the PSP IP modules. Reviewed-by:
-
Christian König authored
Instead of repeating this multiple times. Signed-off-by:
Monk Liu <monk.liu@amd.com> Signed-off-by:
-
Christian König authored
Reserve VA space at the top for older generations as well. Signed-off-by:
-
Christian König authored
1MB should be more than enough, currently we use about 8K. Signed-off-by:
-
Samuel Li authored
Add display to the name for consistency. Signed-off-by:
Samuel Li <Samuel.Li@amd.com> Acked-by:
-
Samuel Li authored
Add display to the name for consistency. Signed-off-by:
-
Samuel Li authored
Add display to the name for consistency. Signed-off-by:
-
Samuel Li authored
Rename as amdgpu_display_update_priority for consistency. Signed-off-by:
-
Samuel Li authored
Add display to the name for consistency. Signed-off-by:
-
Samuel Li authored
Add display to the name for consistency. Signed-off-by:
-
Samuel Li authored
Add display to the name for consistency. Signed-off-by:
-
Samuel Li authored
Add display to the name for consistency. Signed-off-by:
-
Samuel Li authored
Add display to the name for consistency. Signed-off-by:
-
Samuel Li authored
Add display to the name for consistency. Signed-off-by:
-
Samuel Li authored
Add display to the name for consistency. Signed-off-by:
-
Samuel Li authored
Add display to the name for consistency. Signed-off-by:
-
Christian König authored
All HDP invalidation and most flush can now be replaced by the generic ASIC function. Signed-off-by:
Chunming Zhou <david1.zhou@amd.com> Signed-off-by:
-
Christian König authored
When ring special operations aren't available we can fallback to the generic ASIC operations. Signed-off-by:
-
Christian König authored
This adds an optional ring to the invalidate_hdp and flush_hdp callbacks. If the ring isn't specified or the emit_wreg function not available the HDP operation will be done with the CPU otherwise by writing on the ring. Signed-off-by:
-
Rex Zhu authored
when Overdrive voltage, need to disable AVFS. when OverDriv engine clock, need to recalculate AVFS voltage by disable/enable avfs feature. Reviewed-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
-
Rex Zhu authored
Delete old OD type code path when populate clk. Reviewed-by:
-
Rex Zhu authored
v2: - check clk against OverDrive limits from VBIOS - set OD flag when user commit the setting. Reviewed-by:
-
