- 16 Mar, 2023 12 commits
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Manivannan Sadhasivam authored
For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI addresses (0x60200000, 0x40200000) specified in the ranges property for I/O region. While at it, let's use the missing 0x prefix for the addresses. Fixes: a1c86c68 ("arm64: dts: qcom: sm8150: Add PCIe nodes") Reported-by:
Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/linux-arm-msm/7c5dfa87-41df-4ba7-b0e4-72c8386402a8@app.fastmail.com/Signed-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230228164752.55682-12-manivannan.sadhasivam@linaro.org
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Manivannan Sadhasivam authored
For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI addresses (0x30200000, 0x32200000, 0x34200000, 0x38200000, 0x3c200000) specified in the ranges property for I/O region. Fixes: 813e8315 ("arm64: dts: qcom: sc8280xp/sa8540p: add PCIe2-4 nodes") Reported-by:
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Manivannan Sadhasivam authored
To maintain the uniformity, let's use the 0x prefix for the values of ranges property. Signed-off-by:
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Manivannan Sadhasivam authored
For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI addresses (0x60200000, 0x40200000, 0x64200000) specified in the ranges property for I/O region. While at it, let's use the missing 0x prefix for the addresses. Fixes: e53bdfc0 ("arm64: dts: qcom: sm8250: Add PCIe support") Reported-by:
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Manivannan Sadhasivam authored
For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI addresses (0x0c200000, 0x0d200000, 0x0e200000) specified in the ranges property for I/O region. While at it, let's also align the entries. Fixes: ed965ef8 ("arm64: dts: qcom: msm8996: add support to pcie") Reported-by:
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Manivannan Sadhasivam authored
For 64KiB of the I/O region, the I/O ports of the legacy PCI devices are located in the range of 0x0 to 0x10000. Hence, fix the bogus PCI address (0x20200000) specified in the ranges property for I/O region. While at it, let's use the missing 0x prefix for the addresses. Fixes: 095bbdd9 ("arm64: dts: qcom: ipq6018: Add pcie support") Reported-by:
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Manivannan Sadhasivam authored
For 64KiB of the I/O region, the I/O ports of the legacy PCI devices are located in the range of 0x0 to 0x10000. Hence, fix the bogus PCI addresses (0x10200000, 0x20200000) specified in the ranges property for I/O region. While at it, let's use the missing 0x prefix for the addresses and align them in a single line. Fixes: 33057e16 ("ARM: dts: ipq8074: Add pcie nodes") Reported-by:
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Manivannan Sadhasivam authored
For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI addresses (0x60200000, 0x40200000) specified in the ranges property for I/O region. While at it, let's use the missing 0x prefix for the addresses. Fixes: 7d1158c9 ("arm64: dts: qcom: sm8550: Add PCIe PHYs and controllers nodes") Reported-by:
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Manivannan Sadhasivam authored
For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI address (0x40200000) specified in the ranges property for I/O region. Fixes: 92e0ee9f ("arm64: dts: qcom: sc7280: Add PCIe and PHY related nodes") Reported-by:
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Manivannan Sadhasivam authored
For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI address (0x1b200000) specified in the ranges property for I/O region. Fixes: b84dfd17 ("arm64: dts: qcom: msm8998: Add PCIe PHY and RC nodes") Reported-by:
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Manivannan Sadhasivam authored
For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI addresses (0x60200000, 0x40200000) specified in the ranges property for I/O region. While at it, let's use the missing 0x prefix for the addresses. Fixes: 42ad2313 ("arm64: dts: qcom: sdm845: Add second PCIe PHY and controller") Fixes: 5c538e09 ("arm64: dts: qcom: sdm845: Add first PCIe controller and PHY") Reported-by:
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Konrad Dybcio authored
Cores 0-3 are CA78C r0p0, cores 4-7 are CX1C r0p0. Use the correct compatibles instead of the placeholder qcom,kryo. Signed-off-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
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- 15 Mar, 2023 28 commits
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Mao Jinlong authored
Add tpdm mm and tpdm prng for sm8250. +---------------+ +-------------+ | tpdm@6c08000 | |tpdm@684C000 | +-------|-------+ +------|------+ | | +-------|-------+ | | funnel@6c0b000| | +-------|-------+ | | | +-------|-------+ | |funnel@6c2d000 | | +-------|-------+ | | | | +---------------+ | +----- tpda@6004000 -----------+ +-------|-------+ | +-------|-------+ |funnel@6005000 | +---------------+ Acked-by:Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by:
Mao Jinlong <quic_jinlmao@quicinc.com> Signed-off-by:
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Vincent Guittot authored
While stressing EAS on my dragonboard RB3, I have noticed that LITTLE cores where never selected as the most energy efficient CPU whatever the utilization level of waking task. energy model framework uses its cost field to estimate the energy with the formula: nrg = cost of the selected OPP * utilization / CPU's max capacity which ends up selecting the CPU with lowest cost / max capacity ration as long as the utilization fits in the OPP's capacity. If we compare the cost of a little OPP with similar capacity of a big OPP like : OPP(kHz) OPP capacity cost max capacity cost/max capacity LITTLE 1766400 407 351114 407 863 big 1056000 408 520267 1024 508 This can be interpreted as the LITTLE core consumes 70% more than big core for the same compute capacity. According to [1], LITTLE consumes 10% less than big core for Coremark benchmark at those OPPs. If we consider that everything else stays unchanged, the dynamic-power-coefficient of LITTLE core should be only 53% of the current value: 290 * 53% = 154 Set the dynamic-power-coefficient of CPU0-3 to 154 to fix the energy model. [1] https://github.com/kdrag0n/freqbench/tree/master/results/sdm845/main Fixes: 0e0a8e35 ("arm64: dts: qcom: sdm845: correct dynamic power coefficients") Signed-off-by:Vincent Guittot <vincent.guittot@linaro.org> Signed-off-by:
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Kathiravan T authored
Add SMEM support by adding required nodes. Signed-off-by:
Kathiravan T <quic_kathirav@quicinc.com> Signed-off-by:
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Kathiravan T authored
Enable the support for download mode to collect the RAM dumps if system crashes, to perform the post mortem analysis. Signed-off-by:
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Kathiravan T authored
Add initial device tree support for the Qualcomm IPQ5332 SoC and MI01.2 board. Signed-off-by:
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Krzysztof Kozlowski authored
status=okay should appear in final place where all required properties are provided, because that makes the code the easiest to read. Move the status from common OnePlus DTSI to board DTS. No functional changes. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by:
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Krzysztof Kozlowski authored
Nodes with unit addresses must have also 'reg' property: sc7280-herobrine-crd.dtb: eud@88e0000: ports:port@0: 'reg' is a required property Fixes: 0b059979 ("arm64: dts: qcom: sc7280: Add EUD dt node and dwc3 connector") Signed-off-by:
Souradeep Chowdhury <quic_schowdhu@quicinc.com> Signed-off-by:
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Krzysztof Kozlowski authored
The bindings expect RPM clock controller subnode to be named 'clock-controller': apq8094-sony-xperia-kitakami-karin_windy.dtb: smd: rpm:rpm-requests: 'rpmcc' does not match any of the regexes: '^regulators(-[01])?$', 'pinctrl-[0-9]+' Signed-off-by:
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Krzysztof Kozlowski authored
The RPM power domain controller does not take XO clock as input (according to bindings and Linux driver): msm8953-xiaomi-vince.dtb: rpm-requests: power-controller: 'clock-names', 'clocks' do not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by:
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Krzysztof Kozlowski authored
The bindings expect RPM clock controller subnode to be named 'clock-controller': msm8953-motorola-potter.dtb: smd: rpm:rpm-requests: 'rpmcc' does not match any of the regexes: '^regulators(-[01])?$', 'pinctrl-[0-9]+' Signed-off-by:
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Krzysztof Kozlowski authored
The SPI controller nodes do not use/allow cs-select property: ipq6018-cp01-c1.dtb: spi@78b5000: Unevaluated properties are not allowed ('cs-select' was unexpected) Signed-off-by: -
Krzysztof Kozlowski authored
The SPI controller nodes do not use/allow label property: apq8096-db820c.dtb: spi@7575000: Unevaluated properties are not allowed ('label' was unexpected) Signed-off-by: -
Krzysztof Kozlowski authored
The SPI controller nodes do not use/allow label property: sdm845-db845c.dtb: spi@888000: Unevaluated properties are not allowed ('label' was unexpected) Signed-off-by: -
Krzysztof Kozlowski authored
The serial node does not use/allow address/size cells: qdu1000-idp.dtb: geniqup@9c0000: serial@99c000: Unevaluated properties are not allowed ('#address-cells', '#size-cells' were unexpected) Fixes: 6bd20c54 ("arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs") Signed-off-by: -
Krzysztof Kozlowski authored
There is only one output port, thus out-ports should not have 'address/size-cells' and unit addresses. 'reg-names' are also not allowed by bindings. qrb5165-rb5.dtb: funnel@6042000: out-ports: '#address-cells', '#size-cells', 'port@0' do not match any of the regexes: 'pinctrl-[0-9]+' qrb5165-rb5.dtb: funnel@6b04000: Unevaluated properties are not allowed ('reg-names' was unexpected) Signed-off-by: -
Krzysztof Kozlowski authored
The SPMI controller (PMIC Arbiter)) does not use nor allow 'cell-index' property: sm8150-microsoft-surface-duo.dtb: spmi@c440000: Unevaluated properties are not allowed ('cell-index' was unexpected) Signed-off-by: -
Bartosz Golaszewski authored
There's a typo in the @<address> part of the uart9 label. Fix it. Fixes: 10d900a8 ("arm64: dts: sm8150: add the QUPv3 high-speed UART node") Signed-off-by:
Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by:
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Manivannan Sadhasivam authored
The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. On SM6350, there is only one LLCC bank available. So let's just pass that as "llcc0_base". Reported-by:
Parikshit Pareek <quic_ppareek@quicinc.com> Tested-by:
Luca Weiss <luca.weiss@fairphone.com> Signed-off-by:
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Manivannan Sadhasivam authored
The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Reported-by:
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Manivannan Sadhasivam authored
The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Reported-by:
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Manivannan Sadhasivam authored
The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Reported-by:
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Manivannan Sadhasivam authored
The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Reported-by:
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Manivannan Sadhasivam authored
The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Reported-by:
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Manivannan Sadhasivam authored
The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. While at it, let's also fix the size of the llcc_broadcast_base to cover the whole region. Reported-by:
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Manivannan Sadhasivam authored
The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. On SC7180, there is only one LLCC bank available. So let's just pass that as "llcc0_base". Reported-by:
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Manivannan Sadhasivam authored
The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. On SDM845, the size of the LLCC bank 0 needs to be reduced to 0x4500 as there are LLCC BWMON registers located after this range. Reported-by:
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Konrad Dybcio authored
Add missing dwc3 quirks from msm-3.18. Unfortunately, none of them make `dwc3-qcom 6af8800.usb: HS-PHY not in L2` go away. Signed-off-by:
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Mukesh Ojha authored
Add a simple-mfd representing IMEM on SM8450 and define the PIL relocation info region, so that post mortem tools will be able to locate the loaded remoteprocs. Signed-off-by:
Mukesh Ojha <quic_mojha@quicinc.com> Reviewed-by:
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