- 26 Sep, 2017 40 commits
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Dmytro Laktyushkin authored
Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
Harry Wentland <Harry.Wentland@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Roman Li authored
- fixing bug in calculation of reg offset for D5VGA_CONTROL Signed-off-by:
Roman Li <Roman.Li@amd.com> Reviewed-by:
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Tony Cheng authored
instead of GC, as after GFX off, GC can be power gated any time Signed-off-by:
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Andrey Grodzovsky authored
Remove extra loop we have for page flips and do flips in same loop we do for surface create/update. Add documentation for synchronization between commits on different crtcs. Rename function to have DM prefix. Signed-off-by:
Andrey Grodzovsky <Andrey.Grodzovsky@amd.com> Reviewed-by:
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Dmytro Laktyushkin authored
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Leo (Sunpeng) Li authored
Calling dcn10_cursor_set_position() before dcn10_cursor_set_attributes() with invalid (0-value) attributes can cause the ASIC to hang. This fix checks that address.quadpart is non-zero within set_position before calling set_attributes. Signed-off-by:
Leo (Sunpeng) Li <sunpeng.li@amd.com> Reviewed-by:
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Andrey Grodzovsky authored
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Andrey Grodzovsky authored
Today we use special interface for flip because of fear of cuncurency issues over dc->current_ctx. This should be no longer an issue when flipping on multiple CRTCs concurently since for fast update (as flip is) no new context is created and the exsisitng is not destroyed. For full updates case when removing or adding streams on once CRTC while flipping on another Adding all current active CRTC's states to the atomic commit in amdgpu_dm_atomic_check will garntee that any such full update commit will wait for completion of any outstanding flip. Signed-off-by:
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Dmytro Laktyushkin authored
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Amy Zhang authored
- Add immediate ABM disable when eDP is disabled - Fix purple screen when ABM is mistakenly enabled on non eDP display Signed-off-by:
Amy Zhang <Amy.Zhang@amd.com> Reviewed-by:
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Andrey Grodzovsky authored
Typo in expresion. Signed-off-by:
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Dmytro Laktyushkin authored
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Amy Zhang authored
- Add BT2020 color space in the set output csc default Signed-off-by:
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Harry Wentland authored
As pointed out by kbuild test robot and Julia Lawall. CC: Julia Lawall <julia.lawall@lip6.fr> CC: Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin authored
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Harry Wentland authored
We should also use it to determine pipe count. Signed-off-by:
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Amy Zhang authored
Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Corbin McElhanney authored
Signed-off-by:
Corbin McElhanney <corbin.mcelhanney@amd.com> Reviewed-by:
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Dmytro Laktyushkin authored
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Charlene Liu authored
DPM0, FCLK=MCLK, single channel bandwidth = dual channel bandwidth for the rest of the DPM levels, single channel bandwidth = 1/2 dual channel bandwidth Signed-off-by:
Charlene Liu <charlene.liu@amd.com> Reviewed-by:
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Harry Wentland authored
Signed-off-by:
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Yongqiang Sun authored
Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin authored
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Andrey Grodzovsky authored
Problem : A race between two adjecent page flips makes the earlier one to release an alocated frame buffer for the subsequent one - since there are 2 frambuffer swapped back and forth between flips, the 'new' fb of the later flip is actually the 'previous' fb for the earlier flip. Fix: Don't set fb->address = 0 in cleanup hook, this is unnecessery and erases the newly cached adress that was set in prepare_fb of the second flip. Signed-off-by:
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Harry Wentland authored
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Anthony Koo authored
- Add functionality to get real hw backlight level as opposed to user level, meaning the level that takes into account backlight ramping over time and backlight reduction due to Varibright - Add backlight optimization which allows for a second OS state that is able to control ABM Signed-off-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
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Ken Chalmers authored
Not necessarily a fatal problem - some monitors will recover and show the stream anyway if link training fails. Signed-off-by:
Ken Chalmers <ken.chalmers@amd.com> Reviewed-by:
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Tony Cheng authored
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Anthony Koo authored
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Leon Elazar authored
Signed-off-by:
Leon Elazar <leon.elazar@amd.com> Reviewed-by:
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Yongqiang Sun authored
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Dmytro Laktyushkin authored
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Harry Wentland authored
If user is using DVI->HDMI dongle dual link signal might pose a problem. Keep single link signal type if clk is lower than max tmds clk. Signed-off-by:
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Andrey Grodzovsky authored
Link index is an unnecessery level of inderection when calling from kernel i2c/aux transfer into DAL. Signed-off-by:
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Harry Wentland authored
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