- 18 Sep, 2020 5 commits
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Philip Cox authored
Add per-process eviction counters to sysfs to keep track of how many eviction events have happened for each process. v2: rename the stats dir, and track all evictions per process, per device. v3: Simplify the stats kobject handling and cleanup. v4: more code cleanup Signed-off-by:
Philip Cox <Philip.Cox@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Philip Cox authored
Extending the module parameter debug_evictions to also print a stack trace when the eviction code path is called. Signed-off-by:
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Xiaoliang Pang authored
Return value should be -EINVAL rather than EINVAL Fixes: f83a9991("drm/amd/powerplay: add Vega10 powerplay support (v5)") Fixes: 2cac05de("drm/amd/powerplay: add the hw manager for vega12 (v4)") Cc: Eric Huang <JinHuiEric.Huang@amd.com> Cc: Evan Quan <evan.quan@amd.com> Reviewed-by:
Evan Quan <evan.quan@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Xiaoliang Pang <dawning.pang@gmail.com> Signed-off-by:
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Ye Bin authored
Fixes coccicheck warnig: drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c:282:12-42: duplicated argument to && or || drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c:3240:12-42: duplicated argument to && or || drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c:5520:7-91: duplicated argument to && or || drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c:5309:86-122: duplicated argument to && or || Fixes: 6725a88f ("drm/amd/display: Add DCN3 DML") Reported-by:
Hulk Robot <hulkci@huawei.com> Signed-off-by:
Ye Bin <yebin10@huawei.com> Signed-off-by:
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Mauro Rossi authored
[Why] linux-next kernel test robot reported the following problem: warning: no previous prototype for 'dce60_get_dp_ref_freq_khz' [-Wmissing-prototypes] [How] mark dce60_get_dp_ref_freq_khz() as static Fixes: 3ecb3b79 "drm/amd/display: dc/clk_mgr: add support for SI parts (v2)" Reported-by:
kernel test robot <lkp@intel.com> Signed-off-by:
Mauro Rossi <issor.oruam@gmail.com> Signed-off-by:
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- 17 Sep, 2020 35 commits
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Likun Gao authored
Add device ID for sienna_cichlid. v2: squash in additional device ids. Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Likun Gao <Likun.Gao@amd.com> Reviewed-by:
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Alex Deucher authored
Switch from magic numbers to defines for AV1 clockgating. Reviewed-by:
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Alex Deucher authored
This adds the AV1 registers. Reviewed-by:
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Alex Deucher authored
Add the VRS registers. Reviewed-by:
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Ye Bin authored
Addresses the following gcc warning with "make W=1": In file included from drivers/gpu/drm/amd/amdgpu/../display/dmub/src/../dmub_srv.h:67:0, from drivers/gpu/drm/amd/amdgpu/../display/dmub/src/dmub_dcn21.c:26: drivers/gpu/drm/amd/amdgpu/../display/dmub/src/../inc/dmub_cmd.h: In function ‘dmub_rb_flush_pending’: drivers/gpu/drm/amd/amdgpu/../display/dmub/src/../inc/dmub_cmd.h:795:12: warning: variable ‘temp’ set but not used [-Wunused-but-set-variable] uint64_t temp; ^ In file included from drivers/gpu/drm/amd/amdgpu/../display/dmub/src/../dmub_srv.h:67:0, from drivers/gpu/drm/amd/amdgpu/../display/dmub/src/dmub_dcn30.c:26: drivers/gpu/drm/amd/amdgpu/../display/dmub/src/../inc/dmub_cmd.h: In function ‘dmub_rb_flush_pending’: drivers/gpu/drm/amd/amdgpu/../display/dmub/src/../inc/dmub_cmd.h:795:12: warning: variable ‘temp’ set but not used [-Wunused-but-set-variable] uint64_t temp; Reported-by: -
Alex Deucher authored
We never unmapped the regiser BAR on failure. Reported-by:
Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by:
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Tom St Denis authored
This register was requested for umr debugging support. Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
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Bhawanpreet Lakha authored
[Why] "Copy GSL groups when committing a new context" patch was accidentally removed during a refactor Patch: 21ffcc94 ("drm/amd/display: Copy GSL groups when committing a new context") [How] Re add it Fixes: b6e881c9 ("drm/amd/display: update navi to use new surface programming behaviour") Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:
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Bhawanpreet Lakha authored
[Why] DTM topology updates happens by default now. This results in DTM warnings when hdcp is not even being enabled. This spams the dmesg and doesn't effect normal display functionality so it is better to log it using DRM_DEBUG_KMS() [How] Change the DRM_WARN() to DRM_DEBUG_KMS() Signed-off-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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Philip Yang authored
Set ttm->sg to NULL after kfree, to avoid memory corruption backtrace: [ 420.932812] kernel BUG at /build/linux-do9eLF/linux-4.15.0/mm/slub.c:295! [ 420.934182] invalid opcode: 0000 [#1] SMP NOPTI [ 420.935445] Modules linked in: xt_conntrack ipt_MASQUERADE [ 420.951332] Hardware name: Dell Inc. PowerEdge R7525/0PYVT1, BIOS 1.5.4 07/09/2020 [ 420.952887] RIP: 0010:__slab_free+0x180/0x2d0 [ 420.954419] RSP: 0018:ffffbe426291fa60 EFLAGS: 00010246 [ 420.955963] RAX: ffff9e29263e9c30 RBX: ffff9e29263e9c30 RCX: 000000018100004b [ 420.957512] RDX: ffff9e29263e9c30 RSI: fffff3d33e98fa40 RDI: ffff9e297e407a80 [ 420.959055] RBP: ffffbe426291fb00 R08: 0000000000000001 R09: ffffffffc0d39ade [ 420.960587] R10: ffffbe426291fb20 R11: ffff9e49ffdd4000 R12: ffff9e297e407a80 [ 420.962105] R13: fffff3d33e98fa40 R14: ffff9e29263e9c30 R15: ffff9e2954464fd8 [ 420.963611] FS: 00007fa2ea097780(0000) GS:ffff9e297e840000(0000) knlGS:0000000000000000 [ 420.965144] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 420.966663] CR2: 00007f16bfffefb8 CR3: 0000001ff0c62000 CR4: 0000000000340ee0 [ 420.968193] Call Trace: [ 420.969703] ? __page_cache_release+0x3c/0x220 [ 420.971294] ? amdgpu_ttm_tt_unpopulate+0x5e/0x80 [amdgpu] [ 420.972789] kfree+0x168/0x180 [ 420.974353] ? amdgpu_ttm_tt_set_user_pages+0x64/0xc0 [amdgpu] [ 420.975850] ? kfree+0x168/0x180 [ 420.977403] amdgpu_ttm_tt_unpopulate+0x5e/0x80 [amdgpu] [ 420.978888] ttm_tt_unpopulate.part.10+0x53/0x60 [amdttm] [ 420.980357] ttm_tt_destroy.part.11+0x4f/0x60 [amdttm] [ 420.981814] ttm_tt_destroy+0x13/0x20 [amdttm] [ 420.983273] ttm_bo_cleanup_memtype_use+0x36/0x80 [amdttm] [ 420.984725] ttm_bo_release+0x1c9/0x360 [amdttm] [ 420.986167] amdttm_bo_put+0x24/0x30 [amdttm] [ 420.987663] amdgpu_bo_unref+0x1e/0x30 [amdgpu] [ 420.989165] amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu+0x9ca/0xb10 [amdgpu] [ 420.990666] kfd_ioctl_alloc_memory_of_gpu+0xef/0x2c0 [amdgpu] Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-by:
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Luben Tuikov authored
Not being able to create amdgpu sysfs attributes is not a fatal error warranting not to continue to try to bring up the display. Thus, if we get an error trying to create amdgpu sysfs attrs, report it and continue on to try to bring up a display. Signed-off-by:
Luben Tuikov <luben.tuikov@amd.com> Acked-by:
Slava Abramov <slava.abramov@amd.com> Signed-off-by:
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Jiansong Chen authored
The firmware provided via MODULE_FIRMWARE appears in the module information. External tools(eg. dracut) may use the list of fw files to include them as appropriate in an initramfs, thus missing declaration will lead to request firmware failure in boot time. Signed-off-by:
Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by:
Tianci Yin <tianci.yin@amd.com> Signed-off-by:
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Shirish S authored
With IOMMU enabled, if SDPIF_MMIO_CNTRL_0 is not set appropriately the system hangs without any trace during S3. To ease debug and to ensure that the failure, if any, was caused by a race conditions that disabled write access to SDPIF_MMIO_CNTRL_0 register, warn the user about it. Signed-off-by:
Shirish S <shirish.s@amd.com> Reviewed-by:
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Evan Quan authored
Update the UMD stable Pstate settings with correct clocks. Signed-off-by:
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Evan Quan authored
SMU FCLK,SOCCLK have dependency on VCN CLKs. Lower VCN values so that FCLK, SOCCLK reflect values set by UMD Stable Pstate. Signed-off-by:
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Evan Quan authored
Since that should be the correct place to put ASIC specific workarounds. Signed-off-by:
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Evan Quan authored
If dc reported by gpio is supported, the power source switching will be performed by pmfw automatically. Thus the power source setting workaround for Navi1x will be not needed. Signed-off-by:
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Evan Quan authored
Process any pending interrupt that occured before driver register for interrupt from GPIO/SMU. Signed-off-by:
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Evan Quan authored
Which tells it's a normal pstate change or memory retraining. Signed-off-by:
Changfeng Zhu <Changfeng.Zhu@amd.com> Acked-by:
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Evan Quan authored
Which tells it's a normal pstate change or memory retraining. Signed-off-by:
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Evan Quan authored
The convertion to "struct dm_pp_clock_range_for_mcif_wm_set_soc15" is totally unnecessary and can be dropped. Signed-off-by:
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Evan Quan authored
Raven never goes to swsmu path. So "adev->smu.ppt_funcs" will be always false. Signed-off-by:
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Evan Quan authored
Drop unneeded "ret". Signed-off-by:
Nirmoy Das <nirmoy.das@amd.com> Signed-off-by:
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Evan Quan authored
Either this was already performed in parent API. Or the table is confirmed to exist. Signed-off-by:
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Evan Quan authored
As these operations are performed in hardware setup and there is actually no race conditions during this period considering: 1. the hardware setup is serial and cannot be in parallel 2. all other operations can be performed only after hardware setup complete. V2: rich the commit log description Signed-off-by:
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Evan Quan authored
As these operations are performed in hardware setup and there is actually no race conditions during this period considering: 1. the hardware setup is serial and cannot be in parallel 2. all other operations can be performed only after hardware setup complete. V2: rich the commit log description Signed-off-by:
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Evan Quan authored
And to fit more accurately what the cod does. Signed-off-by:
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Evan Quan authored
The workaround can be applied only with UCLK DPM enabled. And expand the workaround to more Navi10 SKUs and also Navi14. Signed-off-by:
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Evan Quan authored
And different workaround will be applied based on hybrid cdr bit. V2: add pmfw version guard to make sure the new workaround applied only with pmfw >= 42.53.0 Signed-off-by: -
Evan Quan authored
By uploading dummy pstate tables. Signed-off-by:
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Evan Quan authored
This dummy reading buffer will be used for the new Navi1x UMC CDR workaround. Signed-off-by:
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Evan Quan authored
Drop the unused message(SMU_MSG_DAL_DISABLE_DUMMY_PSTATE_CHANGE). And do not apply this workaround when the max uclk frequency is greater than 750Mhz. Signed-off-by:
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Evan Quan authored
That's where the uclk dpm get enabled and then the uclk cdr workaround can be applied. Signed-off-by:
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Evan Quan authored
This is needed for Navi1X only. And it may help for display missing or hang issue seen on some high resolution monitors. V2: no UCLK DPM enablement for Navi10 A0 secure SKU Signed-off-by:
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Evan Quan authored
So that ASIC specific actions can be added. V2: better namings Signed-off-by:
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