- 15 May, 2024 29 commits
-
-
Jani Nikula authored
Most other PCI ID macros use platform acronyms. Follow suit for PNV. Add INTEL_PNV_IDS() to identify all PNVs. Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: linux-pci@vger.kernel.org Reviewed-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by:
Bjorn Helgaas <bhelgaas@google.com> Link: https://patchwork.freedesktop.org/patch/msgid/5f9b34a2cd388244be03263a5147776bfe64d5ac.1715340032.git.jani.nikula@intel.comSigned-off-by:
Jani Nikula <jani.nikula@intel.com>
-
Ville Syrjälä authored
Having the plane WM/DDB regitster write functions in skl_watermarks.c is rather annoying when trying to implement DSB based plane updates. Move them into the respective files that handle all other plane register writes. Less places where I need to worry about the DSB vs. MMIO decisions. The downside is that we spread the wm struct details a bit further afield. But if that becomes too annoying we can probably abstract things a bit more with a few extra functions. Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240510152329.24098-17-ville.syrjala@linux.intel.comReviewed-by:
-
Ville Syrjälä authored
Get rid of skl_ddb_entry_write() and skl_write_wm_level() and just call intel_de_write_fw() directly. This is prep work towards DSB based plane updates where these wrappers are more of a hinderance. Done with cocci mostly: @@ expression D, R, L; @@ - skl_write_wm_level(D, R, L) + intel_de_write_fw(D, R, skl_plane_wm_reg_val(L)) @@ expression D, R, B; @@ - skl_ddb_entry_write(D, R, B) + intel_de_write_fw(D, R, skl_plane_ddb_reg_val(B)) Signed-off-by:
-
Ville Syrjälä authored
Extract helpers to calculate the final wm/ddb register values for skl+. Will allow me to more cleanly remove the register write wrappers for these registers. Signed-off-by:
-
Ville Syrjälä authored
Currently every skl+ plane register defines some intermediate macros to calculate the final register offset. Pull all of that into common macros, simplifying the final register offset stuff into just five defines: - raw register offsets for the planes 1 and 2 on pipes A and B - the final parametrized macro v2: Rebase Signed-off-by:
-
Ville Syrjälä authored
A few extra tabs have snuck into the skl+ plane register bit definitions. Remove them. v2: Rebase Reviewed-by:
-
Ville Syrjälä authored
A couple of PLANE_WM bits were still using the hand rolled (1<<N) form. Replace with REG_BIT(). v2: Rebase Reviewed-by:
-
Ville Syrjälä authored
Rearrange the plane skl+ universal plane register definitions: - keep everything related to the same register in one place - sort based on register offset - unify the whitespace/etc a bit v2: Define register contents after all offsets (Jani) Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by:
-
Ville Syrjälä authored
We only need register defines for the first two planes on the first two pipes. Nuke everything else. v2: Drop a few more that snuck through Reviewed-by: Jani Nikula <jani.nikula@intel.com> #v1 Signed-off-by:
-
Ville Syrjälä authored
Stop hand rolling PLANE_CTL and PLANE_SURF for the third plane and just use the real thing. Cc: Zhenyu Wang <zhenyuw@linux.intel.com> CC: Zhi Wang <zhi.wang.linux@gmail.com> Signed-off-by:
-
Ville Syrjälä authored
Stop hand rolling PLANE_KEY*() register defines and just use the real thing. Cc: Zhenyu Wang <zhenyuw@linux.intel.com> CC: Zhi Wang <zhi.wang.linux@gmail.com> Signed-off-by:
-
Ville Syrjälä authored
Stop hand rolling PLANE_AUX_OFFSET() and just use the real thing. Cc: Zhenyu Wang <zhenyuw@linux.intel.com> CC: Zhi Wang <zhi.wang.linux@gmail.com> Signed-off-by:
-
Ville Syrjälä authored
Stop hand rolling PLANE_AUX_DIST() and just use the real thing. Cc: Zhenyu Wang <zhenyuw@linux.intel.com> CC: Zhi Wang <zhi.wang.linux@gmail.com> Signed-off-by:
-
Ville Syrjälä authored
On SKL+ the watermark/DDB registers are proper per-plane registers. Move the definitons to their respective files. Cc: Zhenyu Wang <zhenyuw@linux.intel.com> CC: Zhi Wang <zhi.wang.linux@gmail.com> Signed-off-by:
-
Ville Syrjälä authored
Move most cursor register definitions into their own file. Declutters i915_reg.h a bit more. Cc: Zhenyu Wang <zhenyuw@linux.intel.com> CC: Zhi Wang <zhi.wang.linux@gmail.com> Signed-off-by:
-
Ville Syrjälä authored
Move most of the SKL+ universal plane register definitions into their own file. Declutters i915_reg.h a bit more. Cc: Zhenyu Wang <zhenyuw@linux.intel.com> CC: Zhi Wang <zhi.wang.linux@gmail.com> Signed-off-by:
-
Ville Syrjälä authored
_MMIO_PLANE_GAMC() is some leftover macro that is never used. Get rid of it. Signed-off-by:
-
Jouni Högander authored
Add panel replay selective update support to debugfs status interface. In case of sink supporting panel replay we will print out: Sink support: PSR = no, Panel Replay = yes, Panel Replay Selective Update = yes and PSR mode will look like this if printing out enabled panel replay selective update: PSR mode: Panel Replay Selective Update Enabled Current PSR and panel replay printouts remain same. Cc: Kunal Joshi <kunal1.joshi@intel.com> Signed-off-by:
Jouni Högander <jouni.hogander@intel.com> Reviewed-by:
Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240510093823.3146455-13-jouni.hogander@intel.com
-
Jouni Högander authored
Part of intel_psr2_config_valid is valid for panel replay. rename it as intel_sel_update_config_valid. Split psr2 specific part and name it as intel_psr2_config_valid. v3: - move early transport check to psr2 specific check - check intel_psr2_config_valid only for non-Panel Replay case v2: - use psr2_global_enabled for panel replay as well - goto unsupported instead of return when global enabled check fails Signed-off-by:
-
Jouni Högander authored
We are re-using PSR module parameters for panel replay. Update module parameter descriptions with panel replay information: enable_psr: -1 (default) == follow what is in VBT 0 == disable PSR/PR 1 == Allow PSR1 and PR full frame update 2 == allow PSR1/PSR2 and PR Selective Update enable_psr2_sel_fetch 0 == disable selective fetch for PSR and PR 1 (default) == allow selective fetch for PSR PR Signed-off-by:
-
Jouni Högander authored
There are some workarounds that are not applicable for panel replay. Do not apply these if panel replay is used. Bspec: 66624, 50422 Signed-off-by:
-
Jouni Högander authored
DP Panel replay uses SRD_STATUS to track it's status despite selective update mode. Bspec: 53370, 68920 v4: - use PSR2_STATUS for eDP Panel Replay - handle intel_psr_wait_exit_locked as well v3: - do not use PSR2_STATUS for PSR1 v2: - use intel_dp_is_edp to differentiate - modify debugfs status as well Signed-off-by:
-
Jouni Högander authored
Currently intel_dp_get_su_granularity doesn't support panel replay. This fix modifies it to support panel replay as well. v4: - use drm_dp_dpcd_readb instead of drm_dp_dpcd_read - ensure return value is 0 if drm_dp_dpcd_readb fails v3: use correct offset for DP_PANEL_PANEL_REPLAY_CAPABILITY v2: rely on PSR definitions on common bits Signed-off-by:
-
Jouni Högander authored
Add new boolean to store panel replay selective update support of sink into intel_psr struct. Detect panel replay selective update support and store it into this new boolean. v3: Clear sink_panel_replay_su_support in intel_dp_detect v2: Merge adding new boolean into this patch Signed-off-by:
-
Jouni Högander authored
Add definitions for panel replay selective update v2: Remove unnecessary Cc from commit message Signed-off-by:
Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240510093823.3146455-6-jouni.hogander@intel.com
-
Jouni Högander authored
We are about to reuse psr2_enabled for panel replay as well. Rename it as sel_update_enabled to avoid confusion. v3: Rebase v2: Rebase Signed-off-by:
-
Jouni Högander authored
We are about to enable Panel Replay Selective update mode. Vsc revision 0x6 for Panel Replay no matter if it is selective update or full frame update mode. Take this into account when preparing VSC SDP package. Signed-off-by:
-
Jouni Högander authored
After setting has_psr for panel replay as well crtc state dump is improperly printing "psr: enabled" for Panel Replay as well. Fix this by checking also has_panel_replay. Fixes: 5afa6e49 ("drm/i915/psr: Set intel_crtc_state->has_psr on panel replay as well") Signed-off-by:
-
Jouni Högander authored
We are going to reuse has_psr2 for panel_replay as well. Rename it as has_sel_update to avoid confusion. v3: do not add has_psr check into psr2 case in intel_dp_compute_vsc_sdp v2: Rebase Signed-off-by:
-
- 14 May, 2024 1 commit
-
-
Luca Coelho authored
The function descriptions are optional and have not yet been added to the DMC wakelock code, so we shouldn't try to use it. Since this is a regression, remove the kernel-doc entry for DMC wakelocks for now. The proper documentation will be added in a future patch. Fixes: 765425f5 ("drm/i915/display: add support for DMC wakelocks") Signed-off-by:
Luca Coelho <luciano.coelho@intel.com> Reviewed-by:
-
- 13 May, 2024 10 commits
-
-
Jani Nikula authored
Nothing in xe needs xe->sb_lock. None of the i915 display code using ->sb_lock gets built with xe, and in any case that would be wrong as xe uses gt->pcode.lock for this. Acked-by:
Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by:
Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240510094313.3422982-2-jani.nikula@intel.comSigned-off-by:
-
Jani Nikula authored
The xe->enabled_irq_mask member has never been used for anything. Acked-by:
-
Ville Syrjälä authored
Rename the fb pinning functions such that their name directly informs us what gets pinned into which address space. Signed-off-by:
-
Ville Syrjälä authored
We use a mix of 'intel_fb' vs. 'ifbdev->fb' in the same function. Both should be pointing at the same thing. Make things less confusing by just getting existing fb from 'ifbdev->fb' at the start and then sticking with the local 'fb' (renamed from the 'intel_fb') until the very end. v2: rebase Signed-off-by:
-
Ville Syrjälä authored
Change intel_fbdev_fb_alloc() to return struct intel_fb instead of struct drm_framebuffer. Let's us eliminate some annoying aliasing variables in the fbdev setup code. v2: Assing the results to the correct variable (Jani) Fix xe's copy Signed-off-by: -
Ville Syrjälä authored
Make the 'fb' pointers const in the pinning code. We never want to mutate these. Also nuke a few aliasing fb vs. intel_fb cases by just using the more specific type everywhere in the same function. Signed-off-by:
-
Uma Shankar authored
WA_14020863754: Corner case with Min Hblank Fix can cause audio hang Issue: Previously a fix was made to avoid issues with extremely small hblanks, called the "Min Hblank Fix". However, this can potentially cause an audio hang. Workaround : During "Audio Programming Sequence" Audio Enabling - When DP mode is enabled Set mmio offset 0x65F1C bit 18 = 1b, before step #1 "Enable audio Presence Detect" During "Audio Programming Sequence" Audio Disabling - When DP mode is enabled Clear mmio offset 0x65F1C bit 18 = 0b, after step #6 "Disable Audio PD (Presence Detect)" If not clearing PD bit, must also not clear 0x65F1C bit 18 (leave = 1b) v2: Update the platform checks (Jani Nikula) v3: Limited the WA to LNL and BMG, added a helper (Matt Roper) v4: Updated the bit naming, fixed redundant if statement Signed-off-by:
Uma Shankar <uma.shankar@intel.com> Reviewed-by:
Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240509053508.2807834-1-uma.shankar@intel.com
-
Suraj Kandpal authored
Write panel override luminance values which helps the TCON decide if tone mapping needs to be enabled or not. Signed-off-by:
Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by:
Sebastian Wick <sebastian.wick@redhat.com> Signed-off-by:
-
Suraj Kandpal authored
As of now whenerver HDR is switched on we use the PWM to change the backlight as opposed to AUX based backlight changes in terms of nits. This patch writes to the appropriate DPCD registers to enable aux based backlight using values in nits. --v2 -Fix max_cll and max_fall assignment [Jani] -Fix the size sent in drm_dpcd_write [Jani] --v3 -Content Luminance needs to be sent only for pre-ICL after that it is directly picked up from hdr metadata [Ville] --v4 -Add checks for HDR TCON cap bits [Ville] -Check eotf of hdr_output_data and sets bits base of that value. --v5 -Fix capability check bits. -Check colorspace before setting BT2020 --v6 -Use intel_dp_has_gamut_dip to check if we have capability to send sdp [Ville] -Seprate filling of all hdr tcon related bits into it's own function. -Check eotf data to make sure we are in HDR mode [Sebastian] --v7 -Fix confusion function name for hdr mode check [Jani] -Fix the condition which tells us if we are in HDR mode or not [Sebastian] --v8 -Call fill_hdr_tcon_param unconditionally as some parameters may not be dependent on the fact if we are in hdr mode or not [Sebastian] -Fix some conditions after change in hdr mode check [Sebastian] Signed-off-by:
-
Suraj Kandpal authored
Drop comments for EDP HDR DPCD registers as the code and conditions will tell us what can be written where. --v2 -Drop the comments altogether instead of just renaming them [Sebastian] Signed-off-by:
Arun R Murthy <arun.r.murthy@intel.com> Signed-off-by:
-
