- 10 Feb, 2013 3 commits
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Linus Walleij authored
Make it harder to do mistakes by introducing the actual defined ABx500 IRQ number into the IRQ cluster definitions. Deduct cluster offset from the GPIO offset to make each cluster coherent. Signed-off-by:Linus Walleij <linus.walleij@linaro.org>
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Lee Jones authored
The ABx500 GPIO controller used to provide a set of virtual contiguous IRQs for use by sub-devices, but they have been removed after a request from Mainline Maintainers. Now the AB8500 core driver deals with almost all IRQ related issues instead. The ABx500 GPIO driver is now only used to convert between GPIO and IRQ numbers which is actually quite difficult, as the ABx500 GPIO's associated IRQs are clustered together throughout the interrupt number space at irregular intervals. To solve this quandary, we have placed the read-in values into the existing cluster information table to use during conversion. Signed-off-by:
Lee Jones <lee.jones@linaro.org> [Moved irq_base removal into this patch] Signed-off-by:
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Lee Jones authored
In its current state the gpio-ab8500 driver looks after some GPIO lines found on the AB8500 MFD chip. It also controls all of its own IRQ handling for these GPIOs by inventing some virtual IRQs and handing those out to sub-devices. There has been quite a bit of controversy over this and it was a contributing factor to the driver being marked as BROKEN in Mainline. The reason for adopting this method was due to added complexity in the hardware. Unusually, each GPIO has two separate IRQs associated with it, one for a rising and a different one for a falling interrupt. Using this method complicates matters further because the GPIO IRQs are actually sandwiched between a bunch of IRQs which are handled solely by the AB8500 core driver. The best way for us to take this forward is to get rid of the virtual IRQs and only hand out the rising IRQ lines. If a sub-driver wishes to request a falling interrupt, they can do so by requesting a rising line in the normal way. They just have to add IRQ_TYPE_EDGE_FALLING or IRQ_TYPE_EDGE_BOTH, if they require both in the flags. Then if a falling IRQ is triggered, the AB8500 core driver will know how to handle the added complexity accordingly. This should greatly simply things. Signed-off-by:
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- 08 Feb, 2013 1 commit
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Linus Walleij authored
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- 07 Feb, 2013 2 commits
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Linus Walleij authored
This removes the __init notation from some of the the exynos 5440 pin controller set-up functions. These functions are called from probe() and as such may be discarded before probe() completes. Cc: Thomas Abraham <thomas.abraham@linaro.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: -
Linus Walleij authored
The set_mode() and get_mode() functions in the abx500 were not mirrored, leading to the wrong GPIO control bits being read out. Cc: Lee Jones <lee.jones@linaro.org> Reported-by:
Patrice Chotard <patrice.chotard@st.com> Signed-off-by:
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- 06 Feb, 2013 3 commits
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Lee Jones authored
This patch will allow the ABX500 Pinctrl driver to be probed when Device Tree is enabled with an appropriate node contained. Signed-off-by:
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Lee Jones authored
Not quite sure how this ever worked. In ab8500_gpio_to_irq() the GPIO for conversion is passed through as the second argument. If GPIO13, which is a valid GPIO for IRQ functionality, was received; it would be rejected by the following guard: GPIO_IRQ_CLUSTER(5, 12, 0); /* GPIO numbers start from 1 */ if (offset >= cluster->start && offset <= cluster->end) /* Valid GPIO for IRQ use */ Signed-off-by: -
Lee Jones authored
Prior to this patch abx500_gpio_probe() would return the return-value of gpiochip_remove() during its error patch regardless of what the actual failure was. So as long as gpiochip_remove() succeeded, probe() would look like it succeeded too. This patch ensures the correct error value is returned and that mutex_destroy() is invoked if gpiochip_add_pin_range() were to fail. Signed-off-by:
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- 05 Feb, 2013 18 commits
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Maxime Ripard authored
Since the pin controller of sunxi chips is represented as a single bank in the driver. Since this is neither convenient nor represented that way in the datasheets, define a custom of_xlate function with the layout <bank pin flag> Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by:
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John Crispin authored
The mapping logic inside ltq_pmx_gpio_request_enable() was broken. This only effected Falcon SoC. Signed-off-by:
Thomas Langer <thomas.langer@lantiq.com> Signed-off-by:
John Crispin <blogic@openwrt.org> Signed-off-by:
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John Crispin authored
The current code only has a stub for falcon_pinconf_dbg_show. This patch adds proper functionality. Signed-off-by:
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John Crispin authored
The Falcon driver only defined the pinconf parameters but did not pass them properly to the underlying api. Signed-off-by:
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John Crispin authored
On the Falcon SoC the bootleds are located on pins 9->14. Signed-off-by:
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John Crispin authored
The template falcon.dtsi lists all 6 pad controllers that can be loaded. Only probe those that have status = "okay"; inside the dts file. Signed-off-by:
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John Crispin authored
When setting the OpenDrain bit we should really honour the argument passed inside the devicetree. Signed-off-by:
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John Crispin authored
While converting the boards inside OpenWrt to OF I noticed that the we are missing a pinconf parameter to set a pin to output. Signed-off-by:
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John Crispin authored
While converting all the boards supported by OpenWrt to OF I noticed that this feature is missing. Adding it makes the devicetrees more readable. Signed-off-by:
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John Crispin authored
The logic of the OD bit was inverted when calling the pinconf get method. Signed-off-by:
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John Crispin authored
The XWAY pinctrl driver invalidly uses the port and not the pin number to work out the registers and bits to be set for the opendrain and pullup/down resistors. Signed-off-by:
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Lee Jones authored
Current failure path neglects to mutex_destroy() before returning an error due to an invalid parameter or an error received from gpiochip_add(). This patch aims to remedy that behaviour. Signed-off-by:
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Lee Jones authored
This patch provides some superficial changes to the driver to aid with readability and maintainability. We're mostly fixing things like white-space errors, spreading out code which as been clumped together impeding readability and comment layout, such as using the new "/**" comment start for function headers etc. No code semantics were harmed in the making of this patch. Signed-off-by:
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Lee Jones authored
Currently in the empty abx500_pin_config_get() function, we're returning -EINVAL, with a comment stating that the reason for the failure is that the function isn't implemented yet. Well there's a proper return code for that. If we use it, we can do away with the comment too, as it would be implied. Signed-off-by:
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Lee Jones authored
The BIT() macro provides a simple and easy to read way of obtaining bit offsets into things like masks and hardware registers. In this patch we're simply replacing all instances of '1 << x' with 'bit(x)'. Signed-off-by:
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Patrice Chotard authored
Add AB8540 sub driver to the ABx500 family, pins, pin groups and gpio range. As the pin controller (also the ABx500 controllers) is an inherent part of the SoC and will prevent boot if not available, select this from the Ux500 SoC Kconfig. Acked-by:
Olof Johansson <olof@lixom.net> Signed-off-by:
Patrice Chotard <patrice.chotard@stericsson.com> Signed-off-by:
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Patrice Chotard authored
Add AB9540 sub driver to the ABx500 family, pins, pin groups and gpio range. As the pin controller (also the ABx500 controllers) is an inherent part of the SoC and will prevent boot if not available, select this from the Ux500 SoC Kconfig. Acked-by:
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Patrice Chotard authored
Add AB8505 sub driver to the ABx5x family. As the pin controller (also the ABx500 controllers) is an inherent part of the SoC and will prevent boot if not available, select this from the Ux500 SoC Kconfig. Acked-by:
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- 01 Feb, 2013 5 commits
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Maxime Ripard authored
Signed-off-by:
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Maxime Ripard authored
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Maxime Ripard authored
Since the Allwinner SoCs variants don't have the same set of pins to handle, we need to declare the pin ranges available. Signed-off-by:
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Maxime Ripard authored
Signed-off-by:
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Maxime Ripard authored
The Allwinner A10 has 9 banks of 32 GPIOs available, so it doesn't fit in the usual 256 limit set by gpio.h. Increase this number to 288. Acked-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
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- 30 Jan, 2013 7 commits
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Patrice Chotard authored
This adds a subdriver for the AB8500 pinctrl portions. As the pin controller (also the ABx500 controllers) is an inherent part of the SoC and will prevent boot if not available, select this from the Ux500 SoC Kconfig. Acked-by:
Stephen Warren <swarren@nvidia.com> Signed-off-by:
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Patrice Chotard authored
This adds the AB8500 core driver, which will be utilized by the follow-on drivers for different ABx500 variants. Sselect the driver from the DBX500_SOC, as this chip is powering and clocking that SoC. Cc: Samuel Ortiz <sameo@linux.intel.com> Signed-off-by:
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Linus Walleij authored
The AB8500 GPIO driver has been marked BROKEN for ages, and we have something better in store: a shiny new pinctrl driver. So let use delete this old driver as the first step. Signed-off-by: -
Linus Walleij authored
This updates the AB8500 register map with defines for a few new chip variants and adds version detection helpers to handle the different variants. Acked-by:
Samuel Ortiz <sameo@linux.intel.com> Signed-off-by:
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Linus Walleij authored
The pin controller is an inherent part of the SoC, without it the system will not boot, thus it needs to be selected from Kconfig. Acked-by:
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Lee Jones authored
The preference is to use '-' instead of '_' in compatible strings. Signed-off-by:
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Sachin Kamat authored
'pinctrl_release' is used only in this file. Hence make it static. Without this patch we get the following sparse error: drivers/pinctrl/core.c:815:6: warning: symbol 'pinctrl_release' was not declared. Should it be static? Signed-off-by:
Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by:
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- 29 Jan, 2013 1 commit
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Maxime Ripard authored
The IP responsible for the muxing on the Allwinner SoCs are also handling the GPIOs on the system. This patch adds the needed driver that relies on the pinctrl driver for most of its operations. The number of pins available for GPIOs operations are already declared in the pinctrl driver, we only need to probe a generic driver to handle the banks available for each SoC. This driver has been tested on a A13-Olinuxino. Signed-off-by:
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