- 28 Sep, 2021 18 commits
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Jimmy Kizito authored
[Why] MST streams share the same link and should share the same encoder. The current availability check may erroneously determine that an encoder is unavailable for MST streams. [How] When checking for link encoder availability, check if an encoder in use shares a link with the stream for which the availability check is being conducted. If the link is shared, then the link encoder should be shared too and will be deemed available. Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Anson Jacob <Anson.Jacob@amd.com> Signed-off-by:
Jimmy Kizito <Jimmy.Kizito@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Meenakshikumar Somasundaram authored
[Why] Link encoder in the link could be null for certain links. [How] If link encoder in the link is null then get the link encoder from the stream. Reviewed-by:
Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Tested-by:
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Wenjing Liu authored
[why] Unify the code which handles the conversion between hw lane setting and dpcd lane setting. v2: squash in unused variable fixes (Alex) Reviewed-by:
Wenjing Liu <wenjing.liu@amd.com> Tested-by:
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Wenjing Liu authored
[why] To support per lane lane setting adjustment, we need to change cur_lane_setting to an array one for each lane as the first step. Reviewed-by:
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David Galiffi authored
[Why] Requested feature to assist with Thermal, Acoustic, Power, and Performance tuning. [How] Add a debug field that will override calculated minimum DRAM clock, if the debug value is larger than the calculate value. Reviewed-by:
Alvin Lee <Alvin.Lee2@amd.com> Acked-by:
David Galiffi <David.Galiffi@amd.com> Tested-by:
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Eric Yang authored
[Why] To prevent unnecessary wake up of DMCUB when ABM is enabled without PSR enabled, driver will notify DMCUB to stop ABM's vertical interrupts if vsync is disabled and steady state is reached. [How] Send inbox message to notify ABM pause based on vsync on/off Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
Eric Yang <Eric.Yang2@amd.com> Tested-by:
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Michael Strauss authored
[WHY] AFMT is unused for DP audio, so powering it on for DP is unnecessary. [HOW] APG block should be powered down instead, however HW defaults to shutdown state when not enabled so no further work is required. Reviewed-by:
Michael Strauss <michael.strauss@amd.com> Tested-by:
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Anthony Koo authored
Acked-by:
Anthony Koo <Anthony.Koo@amd.com> Tested-by:
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Wenjing Liu authored
[why] 128b/132b uses the vpg instance assigned to hpo dp stream encoder. The current vpg used is assigned to dio stream encoder. This is incorrect and cause display black screen because the actual vpg is powered off. Reviewed-by:
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Hawking Zhang authored
didn't read the value of mmCP_HQD_QUANTUM from correct register offset Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Le Ma <Le.Ma@amd.com> Signed-off-by:
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Tao Zhou authored
In ras poison mode, umc uncorrectable error will be ignored until the corrupted data consumed by another ras module (such as gfx, sdma). v2: update the debug message and replace dev_warn with dev_info. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
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Tao Zhou authored
Add RAS poison supported flag and tell PSP RAS TA about the info. v2: rename poison mode to poison supported, we can also disable poison mode even we support it. print value of poison supported if ras feature enablement fails. Signed-off-by: -
Tao Zhou authored
Add ras poison mode query interface for UMC. Signed-off-by:
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Tao Zhou authored
Add ras poison mode query interface for DF. v2: replace RREG32_PCIE with RREG32_SOC15. Signed-off-by:
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Candice Li authored
Updated invoke to use new common TA structure similarily to load/unload. Signed-off-by:
Candice Li <candice.li@amd.com> Reviewed-by:
John Clements <john.clements@amd.com> Signed-off-by:
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Praful Swarnakar authored
[Why] ASSR is dependent on Signed PSP Verstage to enable Content Protection for eDP panels. Unsigned PSP verstage is used during development phase causing ASSR to FAIL. As a result, link training is performed with DP_PANEL_MODE_DEFAULT instead of DP_PANEL_MODE_EDP for eDP panels that causes display flicker on some panels. [How] - Do not change panel mode, if ASSR is disabled - Just report and continue to perform eDP link training with right settings further. Signed-off-by:
Praful Swarnakar <Praful.Swarnakar@amd.com> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Leslie Shi authored
gmc_v{9,10}_0_gart_disable() isn't called matched with correspoding gart_enbale function in SRIOV case. This will lead to gart.bo pin_count leak on driver unload. Cc: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:Leslie Shi <Yuliang.Shi@amd.com> Signed-off-by:
Guchun Chen <guchun.chen@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Dave Airlie authored
Merge tag 'amd-drm-next-5.16-2021-09-27' of https://gitlab.freedesktop.org/agd5f/linux into drm-next amd-drm-next-5.16-2021-09-27: amdgpu: - RAS improvements - BACO fixes - Yellow Carp updates - Misc code cleanups - Initial DP 2.0 support - VCN priority handling - Cyan Skillfish updates - Rework IB handling for multimedia engine tests - Backlight fixes - DCN 3.1 power saving improvements - Runtime PM fixes - Modifier support for DCC image stores for gfx 10.3 - Hotplug fixes - Clean up stack related warnings in display code - DP alt mode fixes - Display rework for better handling FP code - Debugfs fixes amdkfd: - SVM fixes - DMA map fixes radeon: - AGP fix From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210927212653.4575-1-alexander.deucher@amd.comSigned-off-by:
Dave Airlie <airlied@redhat.com>
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- 24 Sep, 2021 1 commit
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git://anongit.freedesktop.org/drm/drm-miscDave Airlie authored
drm-misc-next for 5.15: UAPI Changes: Cross-subsystem Changes: Core Changes: Driver Changes: - Conversions to dev_err_probe() helper - rockchip: Various build improvements, Use DRM_BRIDGE_ATTACH_NO_CONNECTOR for LVDS and RGB - panel: New panel-edp driver Signed-off-by:
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- 23 Sep, 2021 21 commits
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Alex Deucher authored
It's not used outside of soc15.c Reviewed-by:
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Lijo Lazar authored
Update the current state as boot state during dpm initialization. During the subsequent initialization, set_power_state gets called to transition to the final power state. set_power_state refers to values from the current state and without current state populated, it could result in NULL pointer dereference. For ex: on platforms where PCI speed change is supported through ACPI ATCS method, the link speed of current state needs to be queried before deciding on changing to final power state's link speed. The logic to query ATCS-support was broken on certain platforms. The issue became visible when broken ATCS-support logic got fixed with commit f9b7f370 ("drm/amdgpu/acpi: make ATPX/ATCS structures global (v2)"). Bug:https://gitlab.freedesktop.org/drm/amd/-/issues/1698Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
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Candice Li authored
All code paths under the EAGAIN path in RAS late init are unused. Signed-off-by:
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John Clements authored
Explicity post warning if cmd is issued against unsupported IP Update to latest RAS TA interface Reviewed-by:
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Philip Yang authored
Device manager releases device-specific resources when a driver disconnects from a device, devm_memunmap_pages and devm_release_mem_region calls in svm_migrate_fini are redundant. It causes below warning trace after patch "drm/amdgpu: Split amdgpu_device_fini into early and late", so remove function svm_migrate_fini. BUG: https://gitlab.freedesktop.org/drm/amd/-/issues/1718 WARNING: CPU: 1 PID: 3646 at drivers/base/devres.c:795 devm_release_action+0x51/0x60 Call Trace: ? memunmap_pages+0x360/0x360 svm_migrate_fini+0x2d/0x60 [amdgpu] kgd2kfd_device_exit+0x23/0xa0 [amdgpu] amdgpu_amdkfd_device_fini_sw+0x1d/0x30 [amdgpu] amdgpu_device_fini_sw+0x45/0x290 [amdgpu] amdgpu_driver_release_kms+0x12/0x30 [amdgpu] drm_dev_release+0x20/0x40 [drm] release_nodes+0x196/0x1e0 device_release_driver_internal+0x104/0x1d0 driver_detach+0x47/0x90 bus_remove_driver+0x7a/0xd0 pci_unregister_driver+0x3d/0x90 amdgpu_exit+0x11/0x20 [amdgpu] Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Philip Yang authored
If svm migration init failed to create pgmap for device memory, set pgmap type to 0 to disable device SVM support capability. Signed-off-by:
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John Clements authored
Update RAS infrastructure to support RAS query for MCA subblocks Reviewed-by:
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Guchun Chen authored
adev->rmmio is set to be NULL in amdgpu_device_unmap_mmio to prevent access after pci_remove, however, in SRIOV case, amdgpu_virt_release_full_gpu will still use adev->rmmio for access after amdgpu_device_unmap_mmio. The patch is to move such SRIOV calling earlier to fini_early stage. Fixes: 07775fc1 ("drm/amdgpu: Unmap all MMIO mappings") Cc: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by:
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Hayden Goodfellow authored
[Why] Currently, the 32bit kernel build fails due to an incorrect string format specifier. ARRAY_SIZE() returns size_t type as it uses sizeof(). However, we specify it in a string as %ld. This causes a compiler error and causes the 32bit build to fail. [How] Change the %ld to %zu as size_t (which sizeof() returns) is an unsigned integer data type. We use 'z' to ensure it also works with 64bit build. Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
Hayden Goodfellow <Hayden.Goodfellow@amd.com> Signed-off-by:
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Aric Cyr authored
This new DC version brings improvements in the following areas: - New firmware version - Fix HPD problems on DCN2 - Fix generic encoder problems and null deferences - Adjust DCN301 watermark - Rework dynamic bpp for DCN3x - Improve link training fallback logic Acked-by:
Aric Cyr <aric.cyr@amd.com> Signed-off-by:
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Anthony Koo authored
Acked-by:
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Jimmy Kizito authored
[Why] Links which are dynamically assigned link encoders have their link encoder set to NULL. [How] Check that a pointer to a link_encoder object is non-NULL before using it. Reviewed-by:
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Meenakshikumar Somasundaram authored
[Why] Need a bit for x86 driver to enable a FW boot option for an upcoming feature. [How] Added a bit in dmub_fw_boot_options for an upcoming feature. Reviewed-by:
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Liu, Zhan authored
[Why] DIG mapping change is causing a blocker [How] Revert the change for now. We will re-implement it later. Reviewed-by:
Zhan Liu <Zhan.Liu@amd.com> Signed-off-by:
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Liu, Zhan authored
[Why] Starting from B0, along with RDPCSTX, RDPCSPIPE registers are also used. [How] Make sure RDPCSPIPE registers are programmed correctly. Reviewed-by:
Charlene Liu <charlene.liu@amd.com> Acked-by:
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Michael Strauss authored
[WHY] Currently causes visible flicker in some scenarios on OLED eDPs Reviewed-by:
Haonan Wang <haonan.wang2@amd.com> Acked-by:
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Guo, Bing authored
Why: Screen sometimes would have artifacts or blink once at the time when bpp is dynamically changed. How: 1. Changed to update PPS infopacket in frame mode instead of immediate mode since other updates for bpp change are double-buffered. 2. Changed double-buffering enablement programming for DCN30 as advised by ASIC team Reviewed-by:
Bing Guo <Bing.Guo@amd.com> Signed-off-by:
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Nikola Cornij authored
[why] If DCN30 watermark calc is used for DCN301, the calculated values are wrong due to the data structure mismatch between DCN30 and DCN301. However, using the original DCN301 watermark values causes underflow. [how] - Add DCN21-style watermark calculations - Adjust DCN301 watermark values to remove the underflow Reviewed-by:
Nikola Cornij <nikola.cornij@amd.com> Signed-off-by:
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Lai, Derek authored
[Why] The change of setting a timer callback on boot for 10 seconds is still working, just lost power down on boot and power down for DCN3. [How] Added power down on boot and power down for DCN3. Reviewed-by:
Derek Lai <Derek.Lai@amd.com> Signed-off-by:
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Jimmy Kizito authored
[Why] Incorrect encoder assignments were being used while applying a new state to hardware. (1) When committing a new state to hardware requires resetting the back-end, the encoder assignments of the current or old state should be used when disabling the back-end; and the encoder assignments for the next or new state should be used when re-enabling the back-end. (2) Link training on hot plug could take over an encoder already in use by another stream without first disabling it. [How] (1) Introduce a resource context 'link_enc_cfg_context' which includes: - a mode to indicate when transitioning from current to next state. - transient encoder assignments to use during this state transition. Update the encoder configuration interface to respond to queries about encoder assignment based on the mode of operation. (2) Check if an encoder is already in use before attempting to perform link training on hot plug. Reviewed-by:
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Jimmy Kizito authored
[Why] Trying to enable multiple displays simultaneously exposed shortcomings with the algorithm for dynamic link encoder assignment. The main problems were: - Assuming stream order remained constant across states would sometimes lead to invalid DIG encoder assignment. - Incorrect logic for deciding whether or not a DIG could support a stream would also sometimes lead to invalid DIG encoder assignment. - Changes in encoder assignment were wholesale while updating of the pipe backend is incremental. This would lead to the hardware state not matching the software state even with valid encoder assignments. [How] The following changes fix the identified problems. - Use stream pointer rather than stream index to track streams across states. - Fix DIG compatibility check by examining the link signal type rather than the stream signal type. - Modify assignment algorithm to make incremental updates so software and hardware states remain coherent. Additionally: - Add assertions and an encoder assignment validation function link_enc_cfg_validate() to detect potential problems with encoder assignment closer to their root cause. - Reduce the frequency with which the assignment algorithm is executed. It should not be necessary for fast state validation. Reviewed-by:
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