- 19 Feb, 2018 40 commits
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Tom St Denis authored
Add missing {} braces. Signed-off-by:Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Tom St Denis authored
Flip the logic of the comparison and remove the redudant variable for the pool address. (v2): Remove {} bracing. Signed-off-by: -
Tom St Denis authored
Correct missing {} style. Signed-off-by: -
Tom St Denis authored
Explicitly return errors in ttm_tt_alloc_page_directory() and ttm_dma_tt_alloc_page_directory() instead of relying on further logic to detect errors. Signed-off-by:
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Tom St Denis authored
(v2): Remove stray ; noticed by Felix Signed-off-by:
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Tom St Denis authored
Correct indentation and {} brace style. Signed-off-by: -
Christian König authored
At least on x86-64 the upper range is purely used by the kernel, avoid creating any ATS mappings there as security precaution and to allow proper page fault reporting in the upper range. v2: remove unused variable Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Christian König authored
This reverts commit 7bdc53f9 and commit 330df03b. Neither are needed any more. Signed-off-by:
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Christian König authored
This reverts commit 2046d46d. Not needed any more. Signed-off-by:
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Christian König authored
Completely pointless, it is the same reservation object as the root PD anyway. Signed-off-by:
Roger He <Hongbo.He@amd.com> Signed-off-by:
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Christian König authored
Using the standard clear turned out to be to inflexible. First of all it is executed on the system queue, together with buffer moves instead on the per VM queue. And second we need to fill in the page tables with more than just zero. We keep the new functionality of initializing the PDEs/PTEs with ATC routing entries intact. v2: update commit message. Signed-off-by:
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Christian König authored
That got mixed up with the encode ring function. Signed-off-by:
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Alex Deucher authored
Previously we just always exposed everything for asics supported by powerplay. Make it a bit more fine grained. In practice this shouldn't change anything. Acked-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
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Alex Deucher authored
This is also supported with the read_sensor API and there were no more users of the get_temperature API. Acked-by:
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Alex Deucher authored
Rather than using the amdgpu_dpm_get_temperature. Both provide access to the temperature. Acked-by:
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Alex Deucher authored
Expose power via hwmon. Acked-by:
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Alex Deucher authored
Expose vddgfx and vddnb via hwmon. Acked-by:
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Alex Deucher authored
Return an error if the user tried to check or set the fan parameters while the card is powered down (e.g., on a PX/HG system for example). This makes the fan consistent with the temperature stuff. Acked-by:
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Christian König authored
Move the CSA area to the top of the VA space to avoid clashing with HMM/ATC in the lower range on GFX9. v2: wrong sign noticed by Roger, rebase on CSA_VADDR cleanup, handle VA hole on GFX9 as well. Signed-off-by:
Monk Liu <monk.liu@amd.com> Signed-off-by:
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Rex Zhu authored
in populate_single_graphic_level for smu7 Reviewed-by:
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Rex Zhu authored
Move configurable profiling parameters to struct profile_mode_setting and initialize current_profile_setting. Reviewed-by:
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Rex Zhu authored
As not support per DPM level optimization, so delete activity_target array. Reviewed-by:
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Rex Zhu authored
And not support perDPM level optimization on Polaris, so delete sclk activity_target array. Reviewed-by:
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Andrey Grodzovsky authored
Dead code, looks obsolete. Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Andrey Grodzovsky authored
They seem to be obsolete. Signed-off-by:
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Harry Wentland authored
Signed-off-by:
Charlene Liu <charlene.liu@amd.com> Signed-off-by:
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John Barberiz authored
- Sequencing bug of not resetting delay on disconnect to default values Signed-off-by:
John Barberiz <jbarberi@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Mikita Lipski authored
Remove aux engine register programming,when freeing the engine as it was a temporary workaround. Signed-off-by:
Mikita Lipski <mikita.lipski@amd.com> Reviewed-by:
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John Barberiz authored
Signed-off-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Leo (Sunpeng) Li authored
Fix: drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/dce110/dce110_hw_sequencer.c: In function ‘dce110_blank_stream’: drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/dce110/dce110_hw_sequencer.c:1008:31: error: unused variable ‘params’ [-Werror=unused-variable] struct encoder_unblank_param params = { { 0 } }; Signed-off-by:Leo (Sunpeng) Li <sunpeng.li@amd.com> Reviewed-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Acked-by:
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Charlene Liu authored
Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Geling Li authored
Signed-off-by:
Geling Li <geling.li@amd.com> Reviewed-by:
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Krunoslav Kovac authored
Signed-off-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by:
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Tony Cheng authored
Signed-off-by:
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Charlene Liu authored
Signed-off-by:
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Dmytro Laktyushkin authored
Directly editing pipe config outside of formula is error prone and results in higher clocks being used when splitting. For this reason we reverted to using bounding box hacking to split. Since sometimes this erroneusly results in higher dpm being required we unhack the bounding box and recalculate to allow dpm0 is possible. Side effect is we will lose some stutter efficiency in non dpm0 cases. This is not a big concern since increased stutter efficiency saves an order of magnitude less power than lower dpm. Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
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Charlene Liu authored
Signed-off-by:
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Arun Pandey authored
Signed-off-by:
Arun Pandey <Arun.Pandey@amd.com> Reviewed-by:
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Charlene Liu authored
Signed-off-by:
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Yongqiang Sun authored
Use tg count in resource pool for further reference. Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
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