- 19 Feb, 2022 7 commits
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Samuel Holland authored
This driver, like several others, uses a chained IRQ for each GPIO bank, and forwards .irq_set_wake to the GPIO bank's upstream IRQ. As a result, a call to irq_set_irq_wake() needs to lock both the upstream and downstream irq_desc's. Lockdep considers this to be a possible deadlock when the irq_desc's share lockdep classes, which they do by default: ============================================ WARNING: possible recursive locking detected 5.17.0-rc3-00394-gc849047c2473 #1 Not tainted -------------------------------------------- init/307 is trying to acquire lock: c2dfe27c (&irq_desc_lock_class){-.-.}-{2:2}, at: __irq_get_desc_lock+0x58/0xa0 but task is already holding lock: c3c0ac7c (&irq_desc_lock_class){-.-.}-{2:2}, at: __irq_get_desc_lock+0x58/0xa0 other info that might help us debug this: Possible unsafe locking scenario: CPU0 ---- lock(&irq_desc_lock_class); lock(&irq_desc_lock_class); *** DEADLOCK *** May be due to missing lock nesting notation 4 locks held by init/307: #0: c1f29f18 (system_transition_mutex){+.+.}-{3:3}, at: __do_sys_reboot+0x90/0x23c #1: c20f7760 (&dev->mutex){....}-{3:3}, at: device_shutdown+0xf4/0x224 #2: c2e804d8 (&dev->mutex){....}-{3:3}, at: device_shutdown+0x104/0x224 #3: c3c0ac7c (&irq_desc_lock_class){-.-.}-{2:2}, at: __irq_get_desc_lock+0x58/0xa0 stack backtrace: CPU: 0 PID: 307 Comm: init Not tainted 5.17.0-rc3-00394-gc849047c2473 #1 Hardware name: Allwinner sun8i Family unwind_backtrace from show_stack+0x10/0x14 show_stack from dump_stack_lvl+0x68/0x90 dump_stack_lvl from __lock_acquire+0x1680/0x31a0 __lock_acquire from lock_acquire+0x148/0x3dc lock_acquire from _raw_spin_lock_irqsave+0x50/0x6c _raw_spin_lock_irqsave from __irq_get_desc_lock+0x58/0xa0 __irq_get_desc_lock from irq_set_irq_wake+0x2c/0x19c irq_set_irq_wake from irq_set_irq_wake+0x13c/0x19c [tail call from sunxi_pinctrl_irq_set_wake] irq_set_irq_wake from gpio_keys_suspend+0x80/0x1a4 gpio_keys_suspend from gpio_keys_shutdown+0x10/0x2c gpio_keys_shutdown from device_shutdown+0x180/0x224 device_shutdown from __do_sys_reboot+0x134/0x23c __do_sys_reboot from ret_fast_syscall+0x0/0x1c However, this can never deadlock because the upstream and downstream IRQs are never the same (nor do they even involve the same irqchip). Silence this erroneous lockdep splat by applying what appears to be the usual fix of moving the GPIO IRQs to separate lockdep classes. Fixes: a59c99d9 ("pinctrl: sunxi: Forward calls to irq_set_irq_wake") Reported-by:Guenter Roeck <linux@roeck-us.net> Signed-off-by:
Samuel Holland <samuel@sholland.org> Reviewed-by:
Jernej Skrabec <jernej.skrabec@gmail.com> Tested-by:
Linus Walleij <linus.walleij@linaro.org>
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Mans Rullgard authored
Avoid printing an error message if getting a regulator fails with EPROBE_DEFER. This can happen if, for example, a regulator supplying one of the main banks is controlled by a PL pin. Signed-off-by:
Mans Rullgard <mans@mansr.com> Acked-by:
Chen-Yu Tsai <wens@csie.org> Link: https://lore.kernel.org/r/20220217131737.10931-1-mans@mansr.comSigned-off-by:
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Linus Walleij authored
Merge tag 'samsung-pinctrl-5.18-2' of https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel Samsung pinctrl drivers changes for v5.18 1. Fix OF reference leak in pinctrl driver probe error path. 2. Correct list of handlers for Exynos850 ALIVE and CMGP pin banks. 3. Accept devicetrees with GPIO pin bank definitions named with a "-gpio-bank" suffix. This is necessary for later Samsung pinctrl bindings dtschema. 4. Convert Samsung pinctrl bindings to dtschema. 5. Add support for Exynos850 and ExynosAutov9 wake-up interrupts. 6. Add support for Tesla FSD SoC.
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Shawn Guo authored
It adds the map of wakeup capable GPIOs and the pins at MPM wake controller on QCM2290, so that these GPIOs can wake up the SoC from vlow/vmin low power mode. Signed-off-by:
Shawn Guo <shawn.guo@linaro.org> Link: https://lore.kernel.org/r/20211122080938.20623-1-shawn.guo@linaro.orgSigned-off-by:
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Jonathan Marek authored
When egpio_enable bit is cleared, the gpio is driven by SSC/LPASS TLMM and the APSS TLMM settings are ignored. Reflect that in the debugfs dump. Signed-off-by:
Jonathan Marek <jonathan@marek.ca> Link: https://lore.kernel.org/r/20220210131210.24605-2-jonathan@marek.caSigned-off-by:
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Jonathan Marek authored
This mirrors egpio support added for sc7280. This change is necessary for gpios 165 to 209 to be driven by APSS. Signed-off-by:
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Linus Walleij authored
Merge tag 'renesas-pinctrl-for-v5.18-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v5.18 - Add MOST (MediaLB I/F) pins on R-Car E3 and D3, - Add support for the new RZ/V2L SoC, - Miscellaneous fixes and improvements.
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- 11 Feb, 2022 12 commits
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Colin Ian King authored
There is a spelling mistake in the documentation. Fix it. Signed-off-by:
Colin Ian King <colin.i.king@gmail.com> Reviewed-by:
Florian Fainelli <f.fainelli@gmail.com> Acked-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220202091551.580372-1-colin.i.king@gmail.comSigned-off-by:
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Jonathan Neuschäfer authored
The name "DS" is defined in arch/x86/um/shared/sysdep/ptrace_64.h, which results in a compiler warning when build-testing on ARCH=um. Rename this driver's "DS" macro to DSTR so avoid this collision. Reported-by:
kernel test robot <lkp@intel.com> Fixes: 3b588e43 ("pinctrl: nuvoton: add NPCM7xx pinctrl and GPIO driver") Signed-off-by:
Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by:
Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20220205155332.1308899-3-j.neuschaefer@gmx.netSigned-off-by:
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Jonathan Neuschäfer authored
When compile-testing on 64-bit architectures, GCC complains about the mismatch of types between the %d format specifier and value returned by ARRAY_LENGTH(). Use %zu, which is correct everywhere. Reported-by:
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kernel test robot authored
drivers/pinctrl/pinctrl-starfive.c:1029:2-3: Unneeded semicolon Remove unneeded semicolon. Generated by: scripts/coccinelle/misc/semicolon.cocci Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Reported-by:
Yang Li <yang.lee@linux.alibaba.com> Link: https://lore.kernel.org/r/20220206003735.GA94316@d6598ff186c2Signed-off-by:
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Chen-Yu Tsai authored
When the constraints and description for bias-pull-{up,down} were added, the constraints were not indented correctly, resulting in them being parsed as part of the description. This effectively nullified their purpose. Move the constraints out of the description block, make each description part of the same associative array as the enum its describing, and reindent them correctly so they take effect. Also add "type: boolean" to the list of valid values. This corresponds to having bias-pull-{up,down} without any arguments. Fixes: 91e7edce ("dt-bindings: pinctrl: mt8195: change pull up/down description") Signed-off-by:Chen-Yu Tsai <wenst@chromium.org> Reviewed-by:
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Horatiu Vultur authored
The blamed commit adds support for irq, but the reqisters for irq are outside of the memory size. They are at address 0x108. Therefore update the memory size to cover all the registers used by the device. Fixes: 01a9350b ("dt-bindings: pinctrl: pinctrl-microchip-sgpio: Add irq support") Signed-off-by:
Horatiu Vultur <horatiu.vultur@microchip.com> Link: https://lore.kernel.org/r/20220204153535.465827-2-horatiu.vultur@microchip.comSigned-off-by:
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Kunihiko Hayashi authored
Add USB device pinmux settings for PXs2 and PXs3 SoCs. Only pins for ports 0 and 1 support USB device mode. Signed-off-by:
Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/1643376903-18623-4-git-send-email-hayashi.kunihiko@socionext.comSigned-off-by:
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Kunihiko Hayashi authored
Current pinmux group for audio in/out assumes 4ch I2S case but the UniPhier AIO hardware also supports 1ch and 2ch I2S. So divide current ain1 group into ain1, ain1_dat2 and ain1_dat4 groups. Divide other ain and aout in the same way. Signed-off-by:
Ryuta NAKANISHI <nakanishi.ryuta@socionext.com> Signed-off-by:
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Kunihiko Hayashi authored
Add missing audio I/O pinmux settings for PXs2 SoC. This adds ain1 4ch pins, ain3 and aout1. Signed-off-by:
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Rayyan Ansari authored
The PM8226 provides 8 MPPs. Add a compatible to support them. Signed-off-by:
Rayyan Ansari <rayyan@ansari.sh> Reviewed-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220124171538.18088-2-rayyan@ansari.shSigned-off-by:
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Rayyan Ansari authored
Document the Device Tree binding for PM8226 MPPs. Signed-off-by:
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Luca Weiss authored
Allow the gpio-reserved-ranges property to be used in dts. Signed-off-by:
Luca Weiss <luca@z3ntu.xyz> Acked-by:
Konrad Dybcio <konrad.dybcio@somainline.org> Acked-by:
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- 08 Feb, 2022 6 commits
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Biju Das authored
Update rzg2l_gpio_register() to use driver data for chip->names and check for gpio-range. This allows reusing the driver for SoC's with different port pin definitions(eg:- RZ/G2UL SoC has fewer ports compared to RZ/G2L and port pin definitions are different). Signed-off-by:
Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220206194614.13209-2-biju.das.jz@bp.renesas.comSigned-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Geert Uytterhoeven authored
Move the msiof* pin groups where they belong. Signed-off-by:
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Geert Uytterhoeven authored
Move the du* pin function where it belongs. Signed-off-by:
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Geert Uytterhoeven authored
Move the sdhi* pin functions where they belong. Signed-off-by:
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Geert Uytterhoeven authored
Rename the MOD_SEL2_* definitions, to match the bitfield order in IPxSRy_* definitions and in MOD_SEL* definitions in other drivers. No changes in generated code. Signed-off-by:
Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Link: https://lore.kernel.org/r/4880e4cbc112ee26569bf29a21c070125461e58d.1642524603.git.geert+renesas@glider.be
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Biju Das authored
RZ/V2L uses the RZ/G2L GPIO and pinctrl driver. Enable the RZ/G2L pinctrl driver if RZ/V2L is enabled. Update the description for RZ/V2L pin control support. Signed-off-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220110134659.30424-8-prabhakar.mahadev-lad.rj@bp.renesas.com Link: https://lore.kernel.org/r/20220206194614.13209-1-biju.das.jz@bp.renesas.comSigned-off-by:
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- 02 Feb, 2022 2 commits
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Horatiu Vultur authored
This patch adds support for ServalT pinctrl, using the ocelot driver as basis. Signed-off-by:
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Horatiu Vultur authored
Add the documentation for the Microsemi ServalT pinmuxing and gpio controller. Signed-off-by:
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- 01 Feb, 2022 1 commit
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Martin Jücker authored
Improve the wake irq message by also printing the bank name and hwirq number that matches this irq number. Signed-off-by:
Martin Jücker <martin.juecker@gmail.com> Link: https://lore.kernel.org/r/20220130232122.GA119248@adroidSigned-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
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- 30 Jan, 2022 5 commits
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Wells Lu authored
Add driver for Sunplus SP7021 SoC. Signed-off-by:
Wells Lu <wellslutw@gmail.com> Link: https://lore.kernel.org/r/1642344734-27229-3-git-send-email-wellslutw@gmail.comSigned-off-by:
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Wells Lu authored
Add dt-bindings header files and documentation for Sunplus SP7021 SoC. Signed-off-by:
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Qianggui Song authored
Add new pinctrl driver for Amlogic's Meson-S4 SoC which share the same register layout as the previous Meson-A1. Acked-by:
Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by:
Qianggui Song <qianggui.song@amlogic.com> Link: https://lore.kernel.org/r/20220113031044.2665-4-qianggui.song@amlogic.comSigned-off-by:
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Qianggui Song authored
Add a new dt-binding header file which documents the detail pin names. Reviewed-by:
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Qianggui Song authored
Add new compatible for Amlogic's Meson-S4 pin controller Reviewed-by:
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- 25 Jan, 2022 4 commits
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Alim Akhtar authored
Adds Tesla FSD SoC specific data to enable pinctrl. FSD SoC has similar pinctrl controller as found in the most Samsung/Exynos SoCs. Cc: linux-fsd@tesla.com Acked-by:
Ajay Kumar <ajaykumar.rs@samsung.com> Signed-off-by:
Alim Akhtar <alim.akhtar@samsung.com> Link: https://lore.kernel.org/r/20220124141644.71052-13-alim.akhtar@samsung.comSigned-off-by:
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Alim Akhtar authored
Add compatible for Tesla Full Self-Driving SoC. The pinctrl hardware IP is similar to what found on most of the Exynos series of SoC, so this new compatible is added in Samsung pinctrl binding. Cc: linux-fsd@tesla.com Signed-off-by:
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Rafał Miłecki authored
BCM4908 has its own pins layout so it needs a custom binding and a Linux driver. Signed-off-by:
Rafał Miłecki <rafal@milecki.pl> Reviewed-by:
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Rafał Miłecki authored
It's hardware block that is part of every SoC from BCM4908 family. Signed-off-by:
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- 24 Jan, 2022 3 commits
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Biju Das authored
Document Renesas RZ/V2L pinctrl bindings. The RZ/V2L SoC is package- and pin-compatible with RZ/G2L. No driver changes are required as the RZ/G2L compatible string "renesas,r9a07g044-pinctrl" will be used as a fallback. Signed-off-by:
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Nikita Yushchenko authored
This adds pins, groups, and functions for MediaLB devices on Renesas R-Car E3 and D3 SoCs. Signed-off-by:
Nikita Yushchenko <nikita.yoush@cogentembedded.com> Link: https://lore.kernel.org/r/20211225191713.2187975-1-nikita.yoush@cogentembedded.comSigned-off-by:
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Geert Uytterhoeven authored
The INTC_IRQx_N pin functions were only documented in preliminary versions of the R-Car M2 Hardware User's Manual, and were never used. This reduces kernel size by 40 bytes. Signed-off-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://lore.kernel.org/r/932834b388887e1ae267e5a852c688c79091a5f9.1640269369.git.geert+renesas@glider.be
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