- 06 Jan, 2012 40 commits
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Bjorn Helgaas authored
Microblaze doesn't need to replace pci_scan_child_bus() or do anything special before pci_bus_add_devices(), so we can use the more generic PCI path in pci_scan_root_bus(). CC: Michal Simek <monstr@monstr.eu> Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com> Signed-off-by:
Jesse Barnes <jbarnes@virtuousgeek.org>
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Bjorn Helgaas authored
Convert from pci_create_bus() to pci_create_root_bus(). This way the root bus resources are correct immediately. This patch doesn't fix a problem because microblaze fixed the resources before scanning the bus, but it makes microblaze more consistent with other architectures. It also allows us to use the pci_scan_root_bus() path safely. CC: Michal Simek <monstr@monstr.eu> Signed-off-by:
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Bjorn Helgaas authored
CC: Michal Simek <monstr@monstr.eu> Signed-off-by:
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Bjorn Helgaas authored
The pci_bus_for_each_resource() iterator sets "res" itself, so there's no need to look it up in the bus->resource[] table. Logically part of 89a74ecc and 8a66da71. CC: Michal Simek <monstr@monstr.eu> Signed-off-by:
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Bjorn Helgaas authored
Convert from pci_create_bus() to pci_create_root_bus(). This way the root bus resources are correct immediately. This fixes the problem of "early" and "header" quirks seeing incorrect root bus resources. We can't use pci_scan_root_bus() because, like x86, ACPI hotplug currently requires pci_bus_add_devices() in a separate host bridge .start() method. v2: fix compile error by using window resource pointer instead CC: Tony Luck <tony.luck@intel.com> Signed-off-by:
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Bjorn Helgaas authored
This doesn't change any functionality, but it makes a subsequent patch slightly simpler. CC: Tony Luck <tony.luck@intel.com> Signed-off-by:
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Bjorn Helgaas authored
Convert from pci_scan_bus() to pci_scan_root_bus() and remove root bus resource fixups. This fixes the problem of "early" and "header" quirks seeing incorrect root bus resources. Note that peer root buses are scanned with pci_scan_bus() (which is now deprecated), so they have the default ioport_resource and iomem_resource resources. This is unchanged from before, but these resources are incorrect, and I don't know how to discover the correct ones. CC: David Howells <dhowells@redhat.com> Signed-off-by:
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Bjorn Helgaas authored
Convert from pci_scan_bus() to pci_scan_root_bus() and remove root bus resource fixups. This fixes the problem of "early" and "header" quirks seeing incorrect root bus resources. CC: Russell King <linux@arm.linux.org.uk> Signed-off-by:
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Bjorn Helgaas authored
Convert from pci_scan_bus() to pci_scan_root_bus() and remove root bus resource fixups. This fixes the problem of "early" and "header" quirks seeing incorrect root bus resources. v2: fix up conversion CC: linux-alpha@vger.kernel.org Signed-off-by:
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Bjorn Helgaas authored
Users of pci_scan_bus_parented() should be converted to use either pci_scan_root_bus() (preferred, but also calls pci_bus_add_devices) or pci_create_root_bus() pci_scan_child_bus() Since pci_scan_bus_parented(), I'm marking it deprecated now and will actually remove it later. Signed-off-by: -
Bjorn Helgaas authored
This converts pci_scan_bus_parented() to use pci_create_root_bus() instead of pci_create_bus(). The new bus still has the default (incorrect) resources, so this patch doesn't help fix that problem, but it does remove one more use of pci_create_bus(). Signed-off-by:
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Bjorn Helgaas authored
I plan to deprecate pci_scan_bus_parented(), so use pci_create_root_bus() directly instead. pci_scan_bus() itself will be removed as soon as all callers are gone, so this is just an interim step. v2: export pci_scan_bus Signed-off-by:
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Bjorn Helgaas authored
"Early" and "header" quirks often use incorrect bus resources because they see the default resources assigned by pci_create_bus(), before the architecture fixes them up (typically in pcibios_fixup_bus()). Regions reserved by these quirks end up with the wrong parents. Here's the standard path for scanning a PCI root bus: pci_scan_bus or pci_scan_bus_parented pci_create_bus <-- A create with default resources pci_scan_child_bus pci_scan_slot pci_scan_single_device pci_scan_device pci_setup_device pci_fixup_device(early) <-- B pci_device_add pci_fixup_device(header) <-- C pcibios_fixup_bus <-- D fill in correct resources Early and header quirks at B and C use the default (incorrect) root bus resources rather than those filled in at D. This patch adds a new pci_scan_root_bus() function that sets the bus resources correctly from a supplied list of resources. I intend to remove pci_scan_bus() and pci_scan_bus_parented() after fixing all callers. Signed-off-by: -
Bjorn Helgaas authored
pci_create_bus() assigns ioport_resource and iomem_resource as the default bus resources, i.e., the entire address space. Architectures fix these later, typically in pcibios_fixup_bus() or after pci_scan_bus_parented() returns, but code that runs in the interim sees incorrect resource information. This patch adds a new pci_create_root_bus() that sets the bus resources correctly from a supplied list of resources. I intend to remove pci_create_bus() after changing all callers. Based on original patch by Deng-Cheng Zhu. Reference: http://www.spinics.net/lists/mips/msg41654.html Reference: https://lkml.org/lkml/2011/8/26/88Signed-off-by:
Deng-Cheng Zhu <dczhu@mips.com> Signed-off-by:
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Bjorn Helgaas authored
Show the bus number and resources for every root bus we create. This will become more interesting when we supply the correct resources instead of using the defaults (ioport_resource and iomem_resource). Signed-off-by:
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Bjorn Helgaas authored
We'd like to supply a list of resources when we create a new PCI bus, e.g., the root bus under a PCI host bridge. These are helpers for constructing that list. These are exported because the plan is to replace this exported interface: pci_scan_bus_parented() with this one: pci_add_resource(resources, ...) pci_scan_root_bus(..., resources) Signed-off-by: -
Ram Pai authored
The SRIOV capability, namely page size and total_vfs of a device are configured during enumeration phase of the device. This can potentially interfere with the PCI operations of the platform, if the IOV capability of the device is not enabled. The following patch postpones the configuration of the IOV capability of the device to a later point, when the IOV capability is explicitly enabled by the device driver. The patch is tested on x86 and power platform. Tested-by:
Donald Dutile <ddutile@redhat.com> Signed-off-by:
Ram Pai <linuxram@us.ibm.com> Signed-off-by:
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Yinghai Lu authored
During debugging pcie hotplug with SRIOV with pcie switch, I found pci_stop_bus_device() is called several times for some child devices. So change original pci_remove_bus_device() to __pci_remove_bus_device(), and make it only do remove work, and add a new pci_remove_bus_device that calls pci_stop_bus_device() one time, and then call __pci_remove_bus_device(). Signed-off-by:
Yinghai Lu <yinghai@kernel.org> Signed-off-by:
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Andreas Herrmann authored
Commit 24d9b70b (x86: Use PCI method for enabling AMD extended config space before MSR method) added a message when IO access to PCI ECS was enabled via access to the NB_CFG PCI register. This can lead to a bogus message like [ 0.365177] Extended Config Space enabled on 0 nodes which is misleading because IO ECS access is subsequently enabled for AMD CPUs (that support this) by modifying the corresponding NB_CFG MSR. Furthermore it's not "Extended Config Space" that is enabled by this register setting. It's the IO access that is enabled for extended configruation space. IMHO the ambiguous message needs to be cancelled. Cc: Jan Beulich <jbeulich@novell.com> Cc: Robert Richter <robert.richter@amd.com> Signed-off-by:
Andreas Herrmann <andreas.herrmann3@amd.com> Signed-off-by:
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Myron Stowe authored
The latency timer is read-only and hardwired to zero for all PCIe devices, both Type 0 and Type 1, so don't bother trying to update it and cluttering the dmesg log with meaningless "setting latency timer to 64" messages. Signed-off-by:
Myron Stowe <myron.stowe@redhat.com> Signed-off-by:
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Myron Stowe authored
This patch removes x86's architecture-specific 'pcibios_set_master()' routine and lets the default PCI core based implementation handle PCI device 'latency timer' setup. No functional change. Signed-off-by:
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Myron Stowe authored
This patch removes sh's architecture-specific 'pcibios_set_master()' routine and lets the default PCI core based implementation handle PCI device 'latency timer' setup. No functional change. Signed-off-by:
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Myron Stowe authored
This patch removes mn10300's architecture-specific 'pcibios_set_master()' routine for ASB2305 and lets the default PCI core based implementation handle PCI device 'latency timer' setup. No functional change. Signed-off-by:
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Myron Stowe authored
This patch removes MIPS' architecture-specific 'pcibios_set_master()' routine and lets the default PCI core based implementation handle PCI device 'latency timer' setup. No functional change. Acked-by:
Ralf Baechle <ralf@linux-mips.org> Signed-off-by:
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Myron Stowe authored
This patch removes frv's architecture-specific 'pcibios_set_master()' routine and lets the default PCI core based implementation handle PCI device 'latency timer' setup. No functional change. Signed-off-by:
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Myron Stowe authored
The 'latency timer' of PCI devices, both Type 0 and Type 1, is setup in architecture-specific code [see: 'pcibios_set_master()']. There are two approaches being taken by all the architectures - check if the 'latency timer' is currently set between 16 and 255 and if not bring it within bounds, or, do nothing (and then there is the gratuitously different PA-RISC implementation). There is nothing architecture-specific about PCI's 'latency timer' so this patch pulls its setup functionality up into the PCI core by creating a generic 'pcibios_set_master()' function using the '__weak' attribute which can be used by all architectures as a default which, if necessary, can then be over-ridden by architecture-specific code. No functional change. Signed-off-by:
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Myron Stowe authored
This patch converts Xtensa's architecture-specific 'pcibios_set_master()' routine to a non-inlined function. This will allow follow on patches to create a generic 'pcibios_set_master()' function using the '__weak' attribute which can be used by all architectures as a default which, if necessary, can then be over- ridden by architecture-specific code. Converting 'pci_bios_set_master()' to a non-inlined function will allow Xtensa's 'pcibios_set_master()' implementation to remain architecture-specific after the generic version is introduced and thus, not change current behavior. No functional change. Signed-off-by:
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Myron Stowe authored
This patch converts UniCore's architecture-specific 'pcibios_set_master()' routine to a non-inlined function. This will allow follow on patches to create a generic 'pcibios_set_master()' function using the '__weak' attribute which can be used by all architectures as a default which, if necessary, can then be over- ridden by architecture-specific code. Converting 'pci_bios_set_master()' to a non-inlined function will allow UniCore's 'pcibios_set_master()' implementation to remain architecture-specific after the generic version is introduced and thus, not change current behavior. No functional change. Signed-off-by:
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Myron Stowe authored
This patch converts TILE's architecture-specific 'pcibios_set_master()' routine to a non-inlined function. This will allow follow on patches to create a generic 'pcibios_set_master()' function using the '__weak' attribute which can be used by all architectures as a default which, if necessary, can then be over-ridden by architecture-specific code. Converting 'pci_bios_set_master()' to a non-inlined function will allow TILE's 'pcibios_set_master()' implementation to remain architecture-specific after the generic version is introduced and thus, not change current behavior. No functional change. Acked-by:
Chris Metcalf <cmetcalf@tilera.com> Signed-off-by:
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Myron Stowe authored
This patch converts SPARC's architecture-specific 'pcibios_set_master()' routine to a non-inlined function. This will allow follow on patches to create a generic 'pcibios_set_master()' function using the '__weak' attribute which can be used by all architectures as a default which, if necessary, can then be over- ridden by architecture-specific code. Converting 'pci_bios_set_master()' to a non-inlined function will allow SPARC's 'pcibios_set_master()' implementation to remain architecture-specific after the generic version is introduced and thus, not change current behavior. No functional change. Signed-off-by:
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Myron Stowe authored
This patch converts PowerPC's architecture-specific 'pcibios_set_master()' routine to a non-inlined function. This will allow follow on patches to create a generic 'pcibios_set_master()' function using the '__weak' attribute which can be used by all architectures as a default which, if necessary, can then be over- ridden by architecture-specific code. Converting 'pci_bios_set_master()' to a non-inlined function will allow PowerPC's 'pcibios_set_master()' implementation to remain architecture-specific after the generic version is introduced and thus, not change current behavior. No functional change. Acked-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by:
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Myron Stowe authored
This patch converts MicroBlaze's architecture-specific 'pcibios_set_master()' routine to a non-inlined function. This will allow follow on patches to create a generic 'pcibios_set_master()' function using the '__weak' attribute which can be used by all architectures as a default which, if necessary, can then be over- ridden by architecture-specific code. Converting 'pci_bios_set_master()' to a non-inlined function will allow MicroBlaze's 'pcibios_set_master()' implementation to remain architecture-specific after the generic version is introduced and thus, not change current behavior. No functional change. Signed-off-by:
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Myron Stowe authored
This patch converts IA64's architecture-specific 'pcibios_set_master()' routine to a non-inlined function. This will allow follow on patches to create a generic 'pcibios_set_master()' function using the '__weak' attribute which can be used by all architectures as a default which, if necessary, can then be over-ridden by architecture- specific code. Converting 'pci_bios_set_master()' to a non-inlined function will allow IA64's 'pcibios_set_master()' implementation to remain architecture- specific after the generic version is introduced and thus, not change current behavior. No functional change. Signed-off-by:
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Myron Stowe authored
This patch converts ARM's architecture-specific inlined 'pcibios_set_master()' routine to a non-inlined function. This will allow follow on patches to create a generic 'pcibios_set_master()' function using the '__weak' attribute which can be used by all architectures as a default which, if necessary, can then be over- ridden by architecture-specific code. Converting 'pci_bios_set_master()' to a non-inlined function will allow ARM's 'pcibios_set_master()' implementation to remain architecture- specific after the generic version is introduced and thus, not change current behavior. Note that ARM also has a non-inlined 'pcibios_set_master()' that is used if CONFIG_PCI_HOST_ITE8152 is defined. This patch does not change any behavior here either. No functional change. Signed-off-by:
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Myron Stowe authored
Currently, pcibios_set_master() is implemented in architecture- specific code. There is nothing architecture-specific about PCI's 'latency timer'. This patch adds a declaration for pcibios_set_master() to PCI's core in preperation for pulling the function itself up into the core. Without the addition of this declaration, subsequent patches that remove inline definitions of pcibios_set_master() would be removing the only declaration of such. No functional change. Signed-off-by:
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Jan Kiszka authored
The new PCI API provides both generic probing for 2.3 masking support and check&mask in the interrupt handler. Acked-by:
Michael S. Tsirkin <mst@redhat.com> Signed-off-by:
Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by:
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Jan Kiszka authored
These new PCI services allow to probe for 2.3-compliant INTx masking support and then use the feature from PCI interrupt handlers. The services are properly synchronized with concurrent config space access via sysfs or on device reset. This enables generic PCI device drivers like uio_pci_generic or KVM's device assignment to implement the necessary kernel-side IRQ handling without any knowledge about device-specific interrupt status and control registers. Acked-by:
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Jan Kiszka authored
pci_block_user_cfg_access was designed for the use case that a single context, the IPR driver, temporarily delays user space accesses to the config space via sysfs. This assumption became invalid by the time pci_dev_reset was added as locking instance. Today, if you run two loops in parallel that reset the same device via sysfs, you end up with a kernel BUG as pci_block_user_cfg_access detect the broken assumption. This reworks the pci_block_user_cfg_access to a sleeping service pci_cfg_access_lock and an atomic-compatible variant called pci_cfg_access_trylock. The former not only blocks user space access as before but also waits if access was already locked. The latter service just returns false in this case, allowing the caller to resolve the conflict instead of raising a BUG. Adaptions of the ipr driver were originally written by Brian King. Acked-by:
Brian King <brking@linux.vnet.ibm.com> Acked-by:
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Gary Hade authored
This assures that a _CRS reserved host bridge window or window region is not used if it is not addressable by the CPU. The new code either trims the window to exclude the non-addressable portion or totally ignores the window if the entire window is non-addressable. The current code has been shown to be problematic with 32-bit non-PAE kernels on systems where _CRS reserves resources above 4GB. Signed-off-by:
Gary Hade <garyhade@us.ibm.com> Reviewed-by:
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Alex Williamson authored
Spec shows this as 1010b = 0xa Signed-off-by:
Alex Williamson <alex.williamson@redhat.com> Signed-off-by:
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