- 20 Apr, 2021 9 commits
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Dave Jiang authored
The devm managed lifetime is incompatible with 'struct device' objects that resides in idxd context. This is one of the series that clean up the idxd driver 'struct device' lifetime. Fix idxd->conf_dev 'struct device' lifetime. Address issues flagged by CONFIG_DEBUG_KOBJECT_RELEASE. Add release functions in order to free the allocated memory at the appropriate time. Reported-by:
Jason Gunthorpe <jgg@nvidia.com> Fixes: bfe1d560 ("dmaengine: idxd: Init and probe for Intel data accelerators") Signed-off-by:
Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/161852985319.2203940.4650791514462735368.stgit@djiang5-desk3.ch.intel.comSigned-off-by:
Vinod Koul <vkoul@kernel.org>
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Dave Jiang authored
The idr is only used for an device id, never to lookup context from that id. Switch to plain ida. Fixes: bfe1d560 ("dmaengine: idxd: Init and probe for Intel data accelerators") Reported-by:
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Dave Jiang authored
The devm managed lifetime is incompatible with 'struct device' objects that resides in idxd context. This is one of the series that clean up the idxd driver 'struct device' lifetime. Remove pcim_* management of the PCI device and the ioremap of MMIO BAR and replace with unmanaged versions. This is for consistency of removing all the pcim/devm based calls. Reported-by:
Dan Williams <dan.j.williams@intel.com> Link: https://lore.kernel.org/r/161852984150.2203940.8043988289748519056.stgit@djiang5-desk3.ch.intel.comSigned-off-by:
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Dave Jiang authored
The devm managed lifetime is incompatible with 'struct device' objects that resides in idxd context. This is one of the series that clean up the idxd driver 'struct device' lifetime. Remove devm managed pci interrupt vectors and replace with unmanged allocators. Reported-by:
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Dave Jiang authored
The devm managed lifetime is incompatible with 'struct device' objects that resides in idxd context. This is one of the series that clean up the idxd driver 'struct device' lifetime. Remove embedding of dma_device and dma_chan in idxd since it's not the only interface that idxd will use. The freeing of the dma_device will be managed by the ->release() function. Reported-by:
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Vinod Koul authored
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YueHaibing authored
commit 765c37d8 ("dmaengine: at_xdmac: rework slave configuration part") left behind this, so can remove it. Signed-off-by:
YueHaibing <yuehaibing@huawei.com> Reviewed-by:
Tudor Ambarus <tudor.ambarus@microchip.com> Acked-by:
Ludovic Desroches <ludovic.desroches@microchip.com> Link: https://lore.kernel.org/r/20210407132543.23652-1-yuehaibing@huawei.comSigned-off-by:
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Colin Ian King authored
There are calls to idxd_cmd_exec that pass a null status pointer however a recent commit has added an assignment to *status that can end up with a null pointer dereference. The function expects a null status pointer sometimes as there is a later assignment to *status where status is first null checked. Fix the issue by null checking status before making the assignment. Addresses-Coverity: ("Explicit null dereferenced") Fixes: 89e3becd ("dmaengine: idxd: check device state before issue command") Signed-off-by:Colin Ian King <colin.king@canonical.com> Acked-by:
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Felipe Balbi authored
No functional changes, just adding a new compatible for a diferent SoC. Signed-off-by:
Felipe Balbi <felipe.balbi@microsoft.com> Link: https://lore.kernel.org/r/20210417061951.2105530-2-balbi@kernel.orgSigned-off-by:
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- 12 Apr, 2021 12 commits
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Dave Jiang authored
A pre-release silicon erratum workaround where wq reset does not clear WQCFG registers was leaked into upstream code. Use wq reset command instead of blasting the MMIO region. This also address an issue where we clobber registers in future devices. Fixes: da32b28c ("dmaengine: idxd: cleanup workqueue config after disabling") Reported-by:
Shreenivaas Devarajan <shreenivaas.devarajan@intel.com> Signed-off-by:
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Dave Jiang authored
Add disabling/clearing of MSIX permission entries on device shutdown to mirror the enabling of the MSIX entries on probe. Current code left the MSIX enabled and the pasid entries still programmed at device shutdown. Fixes: 8e50d392 ("dmaengine: idxd: Add shared workqueue support") Signed-off-by:
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Hao Fang authored
s/Hisilicon/HiSilicon/g. It should use capital S, according to the official website. Signed-off-by:
Hao Fang <fanghao11@huawei.com> Acked-by:
Zhangfei Gao <zhangfei.gao@linaro.org> Link: https://lore.kernel.org/r/1617277820-26971-1-git-send-email-fanghao11@huawei.comSigned-off-by:
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Jiapeng Chong authored
Fix the following clang warning: drivers/dma/qcom/hidma.c:94:20: warning: unused function 'to_hidma_desc' [-Wunused-function]. Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Signed-off-by:
Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Link: https://lore.kernel.org/r/1617270816-36400-1-git-send-email-jiapeng.chong@linux.alibaba.comSigned-off-by:
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Dan Carpenter authored
Add a missing put_device(&pdev->dev) if the call to dma_async_device_register(dma); fails. Fixes: 905ca51e ("dmaengine: plx-dma: Introduce PLX DMA engine PCI driver skeleton") Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by:
Logan Gunthorpe <logang@deltatee.com> Link: https://lore.kernel.org/r/YFnq/0IQzixtAbC1@mwandaSigned-off-by:
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Dinghao Liu authored
pm_runtime_get_sync() will increase the runtime PM counter even it returns an error. Thus a pairing decrement is needed to prevent refcount leak. Fix this by replacing this API with pm_runtime_resume_and_get(), which will not change the runtime PM counter on error. Signed-off-by:
Dinghao Liu <dinghao.liu@zju.edu.cn> Acked-by:
Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20210409082805.23643-1-dinghao.liu@zju.edu.cnSigned-off-by:
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Lv Yunlong authored
In the first list_for_each_entry() macro of dma_async_device_register, it gets the chan from list and calls __dma_async_device_channel_register (..,chan). We can see that chan->local is allocated by alloc_percpu() and it is freed chan->local by free_percpu(chan->local) when __dma_async_device_channel_register() failed. But after __dma_async_device_channel_register() failed, the caller will goto err_out and freed the chan->local in the second time by free_percpu(). The cause of this problem is forget to set chan->local to NULL when chan->local was freed in __dma_async_device_channel_register(). My patch sets chan->local to NULL when the callee failed to avoid double free. Fixes: d2fb0a04 ("dmaengine: break out channel registration") Signed-off-by:
Lv Yunlong <lyl2019@mail.ustc.edu.cn> Reviewed-by:
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Andy Shevchenko authored
Some architectures do not provide devm_*() APIs. Hence make the driver dependent on HAVE_IOMEM. Fixes: dbde5c29 ("dw_dmac: use devm_* functions to simplify code") Reported-by:
kernel test robot <lkp@intel.com> Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by:
Viresh Kumar <viresh.kumar@linaro.org> Link: https://lore.kernel.org/r/20210324141757.24710-1-andriy.shevchenko@linux.intel.comSigned-off-by:
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Dave Jiang authored
WQ size can only be changed when the device is disabled. Current code allows change when device is enabled but wq is disabled. Change the check to detect device state. Fixes: c52ca478 ("dmaengine: idxd: add configuration component of driver") Signed-off-by:
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Dave Jiang authored
The operation capability register is 256bits. The current output only prints out the first 64bits. Fix to output the entire 256bits. The current code omits operation caps from IAX devices. Fixes: c52ca478 ("dmaengine: idxd: add configuration component of driver") Reported-by:
Lucas Van <lucas.van@intel.com> Signed-off-by:
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Dave Jiang authored
The delta_rec_size and crc_val in the completion record should be 32bits and not 16bits. Fixes: bfe1d560 ("dmaengine: idxd: Init and probe for Intel data accelerators") Reported-by:
Nikhil Rao <nikhil.rao@intel.com> Signed-off-by:
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Dave Jiang authored
Current code blindly writes over the SWERR and the OVERFLOW bits. Write back the bits actually read instead so the driver avoids clobbering the OVERFLOW bit that comes after the register is read. Fixes: bfe1d560 ("dmaengine: idxd: Init and probe for Intel data accelerators") Reported-by:
Sanjay Kumar <sanjay.k.kumar@intel.com> Signed-off-by:
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- 16 Mar, 2021 18 commits
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Gustavo Pimentel authored
Currently, is missing a null check on a pcim_iomap_table() return value and this can lead to a null pointer dereference if the desired BAR wasn't mapped previously. Fix this by adding a null check and returning -ENOMEM. Addresses-Coverity: ("Dereference null return") Signed-off-by:Gustavo Pimentel <gustavo.pimentel@synopsys.com> Link: https://lore.kernel.org/r/bc5e6b8632c84660bb6dae454980e9419992ed14.1613674948.git.gustavo.pimentel@synopsys.comSigned-off-by:
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Gustavo Pimentel authored
Reverting the applied patch because it caused a regression on ARC700 platform (32 bits). Fixes: 05655541 ("dmaengine: dw-edma: Fix scatter-gather address calculation") Signed-off-by:
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Gustavo Pimentel authored
To keep code consistent, some comments with dma keyword written in lower case are now in upper case. Signed-off-by:
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Gustavo Pimentel authored
When the driver is compiled as a module and loaded if we try to unload it, the Kernel shows a crash log. This Kernel crash is due to the dma_async_device_unregister() call done after deleting the channels, this patch fixes this issue. Signed-off-by:
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Gustavo Pimentel authored
Move struct dentry variable from static definition (dw-edma-v0-debugfs.c) into dw_edma struct (dw-edma-core.h) Also the variable was renamed from base_dir to debugfs. Signed-off-by:
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Gustavo Pimentel authored
Changes the linked list and data blocks offset and sizes to follow the recommendation given by the hardware team for the IPK solution. Although the previous data blocks offset and sizes are still valid and functional, using them that might present some issues related to the IPK solution, since this solution is based on FPGA and might be subjected to timmings constrains. Signed-off-by:
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Gustavo Pimentel authored
In the previous implementation, the driver assumed that there existed only two memory spaces that would equally distribute the amount of read/write channels. This might not be the case on some other implementations, therefore this patch change this requirement so that each write/read channel has its own linked list and data space well defined, which allows different sizes and locations. Signed-off-by:
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Gustavo Pimentel authored
In the driver code structure, I tried to keep the code style consistency by writing the write channels instructions first, and then follow by the read channels instructions, mimicking the hardware implementation. However, this code style failed in some cases. This patch fixes that and no functional changes are expected. Signed-off-by:
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Gustavo Pimentel authored
It was added some extra checks to ensure that the driver doesn't try to use more DMA channels than actually are available in hardware. Signed-off-by:
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Gustavo Pimentel authored
Add device_prep_interleave_dma() support to Synopsys DMA driver. This feature implements a similar data transfer mechanism to the scatter-gather implementation. Signed-off-by:
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Gustavo Pimentel authored
The latest eDMA IP development implements a Vendor-Specific Extended Capability that contains the eDMA BAR, offset, map format, and the number of read/write channels available. Signed-off-by:
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Gustavo Pimentel authored
Add pci_find_vsec_capability() to locate a Vendor-Specific Extended Capability with the specified VSEC ID. The Vendor-Specific Extended Capability (VSEC) allows one or more proprietary capabilities defined by the vendor which aren't standard or shared between vendors. Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com> Link: https://lore.kernel.org/r/d89506834fb11c6fa0bd5d515c0dd55b13ac6958.1613674948.git.gustavo.pimentel@synopsys.comSigned-off-by:
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Gustavo Pimentel authored
Add support for the HDMA feature. This new feature enables the current eDMA IP to use a deeper prefetch of the linked list, which reduces the algorithm execution latency observed when loading the elements of the list, causing more stable and higher data transfer. Signed-off-by:
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Gustavo Pimentel authored
Fix comments offset characters' alignment to follow the same structure of similar comments. Signed-off-by:
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Gustavo Pimentel authored
Add writeq() and readq() for 64 bits architures support. Supporting these two functions will allow the write or the read of eDMA 64 bits registers at once instead of having two consecutive operations. Also, this improvement will allow the PCI optimization transaction messages, which will generate a 64 bits message instead of two messages of 32 bits. Signed-off-by:
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Lars-Peter Clausen authored
The Xilinx dmaengine driver uses a tasklet to process completed descriptors and execute their callbacks. Currently consumers of the DMA channel have to no method of synchronization against this tasklet when using the Xilinx dmaengine drivers. This can lead to race conditions when the consumer frees resources that are accessed in the callback before the tasklet has finished running. It is not enough to just call dmaengine_terminal_all() since on a multi-processor system the tasklet can run concurrently to it and might call the callback after dmaengine_terminate_all() has already finished. To mitigate this issue implement the synchronize() callback for the driver, which will wait until the tasklet has finished. Signed-off-by:
Lars-Peter Clausen <lars@metafoo.de> Link: https://lore.kernel.org/r/20210313125311.4823-1-lars@metafoo.deSigned-off-by:
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Laurent Pinchart authored
The active descriptor pointer is accessed from different contexts, including different interrupt handlers, and its access must be protected by the channel's lock. This wasn't done in the done IRQ handler. Fix it. Signed-off-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://lore.kernel.org/r/20210307040629.29308-3-laurent.pinchart@ideasonboard.comSigned-off-by:
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Laurent Pinchart authored
When multiple channels are part of a video group, the transfer is triggered only when all channels in the group are ready. The logic to do so is incorrect, as it causes the descriptors for all channels but the last one in a group to not being pushed to the hardware. Fix it. Signed-off-by:
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- 06 Mar, 2021 1 commit
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Linus Torvalds authored
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