- 15 Apr, 2021 40 commits
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Joseph Greathouse authored
If we skipped loading MEC2 firmware separately from MEC, then MEC2 will be running the same firmware image. Copy the MEC version and feature numbers into MEC2 version and feature numbers. This is needed for things like GWS support, where we rely on knowing what version of firmware is running on MEC2. Leaving these MEC2 entries blank breaks our ability to version-check enables and workarounds. Signed-off-by:
Joseph Greathouse <Joseph.Greathouse@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Xiaojian Du authored
This patch is to add the callback to get the bootup values for renoir. Signed-off-by:
Xiaojian Du <Xiaojian.Du@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Acked-by:
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Xiaojian Du authored
This patch is to update the atomfirmware header for smu12. v2: remove some unnecessary members Signed-off-by:
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Felix Kuehling authored
ROCm user mode has acquired VMs from DRM file descriptors for as long as it supported the upstream KFD. Legacy code to support older versions of ROCm is not needed any more. Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Signed-off-by:
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Ramesh Errabolu authored
drm/amdgpu: Use iterator methods exposed by amdgpu_res_cursor.h in building SG_TABLE's for a VRAM BO Extend current implementation of SG_TABLE construction method to allow exportation of sub-buffers of a VRAM BO. This capability will enable logical partitioning of a VRAM BO into multiple non-overlapping sub-buffers. One example of this use case is to partition a VRAM BO into two sub-buffers, one for SRC and another for DST. Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Ramesh Errabolu <Ramesh.Errabolu@amd.com> Signed-off-by:
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Luben Tuikov authored
Add back the double-sscanf so that both decimal and hexadecimal values could be read in, but this time invert the scan so that hexadecimal format with a leading 0x is tried first, and if that fails, then try decimal format. Also use a logical-AND instead of nesting double if-conditional. See commit "drm/amdgpu: Fix a bug for input with double sscanf" Cc: Alexander Deucher <Alexander.Deucher@amd.com> Cc: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Luben Tuikov <luben.tuikov@amd.com> Reviewed-by:
John Clements <john.clements@amd.com> Signed-off-by:
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Kenneth Feng authored
add ASPM support on polaris Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
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Kenneth Feng authored
enable ASPM on vega to save the power without the performance hurt. Signed-off-by:
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Kenneth Feng authored
enable ASPM on navi1x for the benifit of system power consumption without performance hurt. Signed-off-by:
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Jack Zhang authored
No need to config GECC feature here for sriov Leave the host drvier to do the configuration job. Signed-off-by:
Jack Zhang <Jack.Zhang1@amd.com> Reviewed-by:
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Lijo Lazar authored
When GFXCLK range is updated in manual/determinism mode, show the updated min/max clock range. Signed-off-by:
Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by:
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Luben Tuikov authored
Imporve the kernel-doc for the RAS sysfs interface. Fix the grammar, fix the context. Cc: Alexander Deucher <Alexander.Deucher@amd.com> Cc: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Luben Tuikov authored
Add bad_page_cnt_threshold to debugfs, an optional file system used for debugging, for reporting purposes only--it usually matches the size of EEPROM but may be different depending on the "bad_page_threshold" kernel module option. The "bad_page_cnt_threshold" is a dynamically computed value. It depends on three things: the VRAM size; the size of the EEPROM (or the size allocated to the RAS table therein); and the "bad_page_threshold" module parameter. It is a dynamically computed value, when the amdgpu module is run, on which further parameters and logic depend, and as such it is helpful to see the dynamically computed value in debugfs. Cc: Alexander Deucher <Alexander.Deucher@amd.com> Cc: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Luben Tuikov authored
Fix if (ret) --> if (!ret), a bug, for "retire_page", which caused the kernel to recall the method with *pos == end of file, and that bounced back with error. On the first run, we advanced *pos, but returned 0 back to fs layer, also a bug. Fix the logic of the check of the result of amdgpu_reserve_page_direct()--it is 0 on success, and non-zero on error, not the other way around. This patch fixes this bug. Cc: Alexander Deucher <Alexander.Deucher@amd.com> Cc: John Clements <john.clements@amd.com> Cc: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Luben Tuikov authored
Remove double-sscanf to scan for %llu and 0x%llx, as that is not going to work! The %llu will consume the "0" in "0x" of your input, and the hex value you think you're entering will always be 0. That is, a valid hex value can never be consumed. On the other hand, just entering a hex number without leading 0x will either be scanned as a string and not match, for instance FAB123, or the leading decimal portion is scanned as the %llu, for instance 123FAB will be scanned as 123, which is not correct. Thus remove the first %llu scan and leave only the %llx scan, removing the leading 0x since %llx can scan either. Addresses are usually always hex values, so this suffices. Cc: Alexander Deucher <Alexander.Deucher@amd.com> Cc: Xinhui Pan <xinhui.pan@amd.com> Cc: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Jinzhou Su authored
Add emit mem sync callback for sdma_v5_2 In amdgpu sync object test, three threads created jobs to send GFX IB and SDMA IB in sequence. After the first GFX thread joined, sometimes the third thread will reuse the same physical page to store the SDMA IB. There will be a risk that SDMA will read GFX IB in the previous physical page. So it's better to flush the cache before commit sdma IB. Signed-off-by:
Jinzhou Su <Jinzhou.Su@amd.com> Reviewed-by:
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Kent Russell authored
Like Arcturus, this isn't available on Aldebaran, so remove it accordingly Signed-off-by:
Kent Russell <kent.russell@amd.com> Reviewed-by:
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Anthony Koo authored
Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
Bindu Ramamurthy <bindur12@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Aric Cyr authored
DC version 3.2.131 brings improvements in multiple areas. In summary, we highlight: -Enhancement for multiple eDP BL control. -Add debug flag to enable eDP ILR by default and debugfs to repress HPD/HPR_RX IRQ. -Fixes for DSC enable sequence,Force vsync flip,hang when psr is enabled etc. -Firmware releases: 0.0.60 0.0.61 Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
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Roman Li authored
[Why] SKIP_CRTC_DISABLE bit should be applicable to all dcn asics not only Raven. [How] Replace check for Raven only with check for all DCNs. Signed-off-by:
Roman Li <Roman.Li@amd.com> Acked-by:
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Jake Wang authored
[WHY & HOW] Driver currently assumes only 1 eDP is connected. Added support for multiple eDP BL control. Signed-off-by:
Jake Wang <haonan.wang2@amd.com> Acked-by:
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Xiaojian Du authored
This patch is to add support for new smu metrics table for vangogh. It will support new and legacy smu metrics table in the meanwhile. New pmfw version is 4.63.36.00, and new smu interface version is #3. v1: check smu pmfw version to determine to use new or legacy smu metrics table v2: check smu interface version to determine to use new or legacy smu metrics table v3: revise wrong symbol Signed-off-by:
Kevin Wang <kevin1.wang@amd.com> Reviewed-by:
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Xiaojian Du authored
This patch is to update the driver interface header for vangogh. New version driver interface header will support new version pmfw (from version 4.63.36.00) which uses new smu metrics table. Signed-off-by:
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Anthony Koo authored
Signed-off-by:
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Lewis Huang authored
[Why] When boot into OS, seamless boot device won't blank stream. Driver update dpp clock when scanline position in vactive will show garbage on screen. [How] Wait for vblank for seamless boot edp display when driver update dpp clock. The apply seamless boot flag will be clear when OS call SetVisibility on. Therefore we only wait for vblank once after boot into OS. Signed-off-by:
Lewis Huang <Lewis.Huang@amd.com> Acked-by:
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Harry Wentland authored
[Why] For debugging reasons it can be beneficial to disable any hotplug and DP shortpulse interrupt handling. [How] Expose a debugfs to set a flag to bypass HPD IRQ handling and skip IRQ handling if flag is set. Signed-off-by:
Harry Wentland <harry.wentland@amd.com> Acked-by:
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Mikita Lipski authored
[why/how] Connecting clock optimization functions to dcn301 HWSS to enable power state enter/exit optimization Signed-off-by:
Mikita Lipski <mikita.lipski@amd.com> Acked-by:
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Mikita Lipski authored
[why & how] Removing unused DSC flag which is incorrect and is not used. We are only using stream->timing.flags.DSC for DSC's current state. Stream state as an input parameter and should not contain any past status flags. Signed-off-by:
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Anthony Wang authored
[Why] Underflow observed when disabling PIP overlay in-game when vsync is disabled, due to OTC master lock not working with game pipe which is immediate flip. [How] When performing a full update, override flip_immediate value to false for all planes, so that flip occurs on vsync. Signed-off-by:
Anthony Wang <anthony1.wang@amd.com> Acked-by:
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Wesley Chalmers authored
[WHY] If no repeaters are found, we do not need or want to attempt to link-train repeaters, as this could cause bugs. Signed-off-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Acked-by:
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Nicholas Kazlauskas authored
[Why] We're always validating DML with simple 422 DSC even if native 422 DSC is in use. [How] Use the mode configuration from the timing. Signed-off-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by:
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Michael Strauss authored
[Why & How] Static cleanup for eDP ILR Support. Signed-off-by:
Michael Strauss <michael.strauss@amd.com> Acked-by:
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Mike Hsieh authored
[Why] DSC is enabled before reset link and potentially cause DSC enable fail problem. [How] Enable DSC after link is reseted Signed-off-by:
Mike Hsieh <chun-wei.hsieh@amd.com> Acked-by:
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Michael Strauss authored
[Why] VBIOS currently sets the max link rate found in eDP 1.4 SUPPORTED_LINK_RATES table If eDP fastboot optimizations are enabled, the link rate remains at max after init [How] Determine optimal link rate during boot, disable seamless boot and eDP fastboot optimizations if link rate optimization is required Signed-off-by:
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Michael Strauss authored
[Why & How] Allow per-asic enablement of ILR feature with debug flag Signed-off-by:
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Eric Huang authored
Due to changes of HW memory model, we need to change Aldebaran MTYPEs to meet HW changes. Signed-off-by:
Eric Huang <jinhuieric.huang@amd.com> Reviewed-by:
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Oak Zeng authored
This new interface passes both virtual and physical address to PSP. It is backward compatible with old interface. v2: use a function to simplify tmr physical address calc (Lijo) Signed-off-by:
Oak Zeng <Oak.Zeng@amd.com> Reviewed-by:
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Oak Zeng authored
Use amdgpu_gmc_vram_pa and amdgpu_gmc_vram_cpu_pa to simplify codes. No logic change. Signed-off-by:
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Oak Zeng authored
Add one function to calculate BO's GPU physical address. And another function to calculate BO's CPU physical address. v2: Use functions vs macros (Christian) Use more proper function names (Christian) Signed-off-by: -
John Clements authored
only output ras error status if an error bit is set or error counter is set Reviewed-by:
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