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  1. 20 Mar, 2014 15 commits
    • Wang Dongsheng's avatar
      fsl/pci: The new pci suspend/resume implementation · 48b16180
      Wang Dongsheng authored 
      If we do nothing in suspend/resume, some platform PCIe ip-block
can't guarantee the link back to L0 state from sleep, then, when
we read the EP device will hang. Only we send pme turnoff message
in pci controller suspend, and send pme exit message in resume, the
link state will be normal.

When we send pme turnoff message in pci controller suspend, the
links will into l2/l3 ready, then, host cannot communicate with
ep device, but pci-driver will call back EP device to save them
state. So we need to change platform_driver->suspend/resume to
syscore->suspend/resume.

So the new suspend/resume implementation, send pme turnoff message
in suspend, and send pme exit message in resume. And add a PME handler,
to response PME & message interrupt.

Change platform_driver->suspend/resume to syscore->suspend/resume.
pci-driver will call back EP device, to save EP state in
pci_pm_suspend_noirq, so we need to keep the link, until
pci_pm_suspend_noirq finish.
Signed-off-by: default avatarWang Dongsheng <dongsheng.wang@freescale.com>
Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
      48b16180
    • Scott Wood's avatar
      Revert "powerpc/watchdog: Don't enable interrupt on PPC64 BookE" · 09394373
      Scott Wood authored 
      This reverts commit 3978bdb4, now that
critical interrupts are properly supported on ppc64 booke.
Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
Cc: Laurentiu Tudor <Laurentiu.Tudor@freescale.com>
Cc: Wim Van Sebroeck <wim@iguana.be>
      09394373
    • Scott Wood's avatar
      powerpc/booke64: Critical and machine check exception support · 609af38f
      Scott Wood authored 
      Add special state saving for critical and machine check exceptions.

Most of this code could be used to handle debug exceptions taken from
kernel space, but actually doing so is outside the scope of this patch.

The various critical and machine check exceptions now point to their
real handlers, rather than hanging the kernel.
Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
      609af38f
    • Scott Wood's avatar
      powerpc/booke64: Add crit/mc/debug support to EXCEPTION_COMMON · 31f71248
      Scott Wood authored 
      Use the proper scratch SPRG and PACA region.  Introduce level-specific
macros to simplify usage and avoid needing to do a bunch of token
pasting throughout EXCEPTION_COMMON().

Now that EXCEPTION_COMMON_DBG() is properly using the debug scratch
register, there's no more need for the caller to move the value to the
GEN scratch first.
Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
      31f71248
    • Scott Wood's avatar
      powerpc/booke64: Remove ints from EXCEPTION_COMMON · 28a3ded1
      Scott Wood authored 
      The ints parameter was used to optionally insert RECONCILE_IRQ_STATE
into EXCEPTION_COMMON.  However, since it came at the end of
EXCEPTION_COMMON, there was no real benefit for it to be there as
opposed to being called separately by the caller of EXCEPTION_COMMON.

The ints parameter was causing some hassle when trying to add an extra
macro layer.  Besides avoiding that, moving "ints" to the caller makes
the code simpler by:
 - avoiding the asymmetry where INTS_RESTORE_HARD is called separately
by the individual exception, but INTS_DISABLE was not
 - removing the no-op INTS_KEEP
 - not having an unnecessary macro parameter

It also turned out to be necessary to delay the INTS_DISABLE
in the case of special level exceptions until after we saved the
old value of PACAIRQHAPPENED.
Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
      28a3ded1
    • Scott Wood's avatar
      powerpc/booke64: Use SPRG_TLB_EXFRAME on bolted handlers · a3dc6207
      Scott Wood authored 
      While bolted handlers (including e6500) do not need to deal with a TLB
miss recursively causing another TLB miss, nested TLB misses can still
happen with crit/mc/debug exceptions -- so we still need to honor
SPRG_TLB_EXFRAME.

We don't need to spend time modifying it in the TLB miss fastpath,
though -- the special level exception will handle that.
Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
Cc: Mihai Caraman <mihai.caraman@freescale.com>
Cc: kvm-ppc@vger.kernel.org
      a3dc6207
    • Scott Wood's avatar
      powerpc/booke64: Use SPRG7 for VDSO · 9d378dfa
      Scott Wood authored 
      Previously SPRG3 was marked for use by both VDSO and critical
interrupts (though critical interrupts were not fully implemented).

In commit 8b64a9df ("powerpc/booke64:
Use SPRG0/3 scratch for bolted TLB miss & crit int"), Mihai Caraman
made an attempt to resolve this conflict by restoring the VDSO value
early in the critical interrupt, but this has some issues:

 - It's incompatible with EXCEPTION_COMMON which restores r13 from the
   by-then-overwritten scratch (this cost me some debugging time).
 - It forces critical exceptions to be a special case handled
   differently from even machine check and debug level exceptions.
 - It didn't occur to me that it was possible to make this work at all
   (by doing a final "ld r13, PACA_EXCRIT+EX_R13(r13)") until after
   I made (most of) this patch. :-)

It might be worth investigating using a load rather than SPRG on return
from all exceptions (except TLB misses where the scratch never leaves
the SPRG) -- it could save a few cycles.  Until then, let's stick with
SPRG for all exceptions.

Since we cannot use SPRG4-7 for scratch without corrupting the state of
a KVM guest, move VDSO to SPRG7 on book3e.  Since neither SPRG4-7 nor
critical interrupts exist on book3s, SPRG3 is still used for VDSO
there.
Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
Cc: Mihai Caraman <mihai.caraman@freescale.com>
Cc: Anton Blanchard <anton@samba.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: kvm-ppc@vger.kernel.org
      9d378dfa
    • Scott Wood's avatar
      powerpc/e6500: Make TLB lock recursive · 82d86de2
      Scott Wood authored 
      Once special level interrupts are supported, we may take nested TLB
misses -- so allow the same thread to acquire the lock recursively.

The lock will not be effective against the nested TLB miss handler
trying to write the same entry as the interrupted TLB miss handler, but
that's also a problem on non-threaded CPUs that lack TLB write
conditional.  This will be addressed in the patch that enables crit/mc
support by invalidating the TLB on return from level exceptions.
Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
      82d86de2
    • Scott Wood's avatar
      powerpc/booke64: Fix exception numbers · c4787d1e
      Scott Wood authored 
      altivec_unavailable was commented as 0xf20 but the code uses 0x200.
Note that 0xf20 is also used by ap_unavailable.

altivec_assist was commented as 0x1700 but the code uses 0x220.

critical_input was commented as 0x580 but the code uses 0x100.

machine_check was commented and implemented as 0x200, which conflicts
with altivec_assist (it only builds because MC_EXCEPTION_PROLOG is
commented out).  Changed to the fixed IVOR value of 0x000.
Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
      c4787d1e
    • Tiejun Chen's avatar
      powerpc/book3e: store crit/mc/dbg exception thread info · 19007b34
      Tiejun Chen authored 
      We need to store thread info to these exception thread info like something
we already did for PPC32.
Signed-off-by: default avatarTiejun Chen <tiejun.chen@windriver.com>
Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
      19007b34
    • Tiejun Chen's avatar
      powerpc/book3e: initialize crit/mc/dbg kernel stack pointers · 160c7324
      Tiejun Chen authored 
      We already allocated critical/machine/debug check exceptions, but
we also should initialize those associated kernel stack pointers
for use by special exceptions in the PACA.
Signed-off-by: default avatarTiejun Chen <tiejun.chen@windriver.com>
Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
      160c7324
    • Wang Dongsheng's avatar
      powerpc/fsl: add PVR definition for E500MC and E5500 · b0b7dcbd
      Wang Dongsheng authored 
      Signed-off-by: default avatarWang Dongsheng <dongsheng.wang@freescale.com>
Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
      b0b7dcbd
    • Zhao Qiang's avatar
      Corenet: Add QE platform support for Corenet · 0f5a8696
      Zhao Qiang authored 
      There is QE on platform T104x, add support.
Call funcs qe_ic_init and qe_init if CONFIG_QUICC_ENGINE is defined.
Signed-off-by: default avatarZhao Qiang <B45475@freescale.com>
[scottwood@freesacle.com: whitespace fix]
Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
      0f5a8696
    • Zhao Qiang's avatar
      QE: split function mpc85xx_qe_init() into two functions. · 706f4aa0
      Zhao Qiang authored 
      New QE doesn't have par_io, it doesn't need to init par_io
for new QE.
Split function mpc85xx_qe_init() into mpc85xx_qe_init()
and mpc85xx_qe_par_io_init().
Call mpc85xx_qe_init() for both new and old while
mpc85xx_qe_par_io_init() after mpc85xx_qe_init() for old.
Signed-off-by: default avatarZhao Qiang <B45475@freescale.com>
Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
      706f4aa0
    • Sebastian Siewior's avatar
      powerpc: 85xx rdb: move np pointer to avoid builderror · b0ad062c
      Sebastian Siewior authored 
      If CONFIG_UCC_GETH or CONFIG_SERIAL_QE is not defined then we get a
warning about an used variable which leads to a build error.
Signed-off-by: default avatarSebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
      b0ad062c
  3. 19 Mar, 2014 6 commits
  5. 07 Mar, 2014 19 commits
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