1. 13 Apr, 2021 1 commit
    • Sergio Paracuellos's avatar
      clk: ralink: add clock driver for mt7621 SoC · 48df7a26
      Sergio Paracuellos authored
      The documentation for this SOC only talks about two
      registers regarding to the clocks:
      * SYSC_REG_CPLL_CLKCFG0 - provides some information about
      boostrapped refclock. PLL and dividers used for CPU and some
      sort of BUS.
      * SYSC_REG_CPLL_CLKCFG1 - a banch of gates to enable/disable
      clocks for all or some ip cores.
      
      Looking into driver code, and some openWRT patched there are
      another frequencies which are used in some drivers (uart, sd...).
      According to all of this information the clock plan for this
      SoC is set as follows:
      - Main top clock "xtal" from where all the rest of the world is
      derived.
      - CPU clock "cpu" derived from "xtal" frequencies and a bunch of
      register reads and predividers.
      - BUS clock "bus" derived from "cpu" and with (cpu / 4) MHz.
      - Fixed clocks from "xtal":
          * "50m": 50 MHz.
          * "125m": 125 MHz.
          * "150m": 150 MHz.
          * "250m": 250 MHz.
          * "270m": 270 MHz.
      
      We also have a buch of gate clocks with their parents:
        * "hsdma": "150m"
        * "fe": "250m"
        * "sp_divtx": "270m"
        * "timer": "50m"
        * "pcm": "270m"
        * "pio": "50m"
        * "gdma": "bus"
        * "nand": "125m"
        * "i2c": "50m"
        * "i2s": "270m"
        * "spi": "bus"
        * "uart1": "50m"
        * "uart2": "50m"
        * "uart3": "50m"
        * "eth": "50m"
        * "pcie0": "125m"
        * "pcie1": "125m"
        * "pcie2": "125m"
        * "crypto": "250m"
        * "shxc": "50m"
      
      With this information the clk driver will provide clock and gates
      functionality from a a set of hardcoded clocks allowing to define
      a nice device tree without fixed clocks.
      Signed-off-by: default avatarSergio Paracuellos <sergio.paracuellos@gmail.com>
      Link: https://lore.kernel.org/r/20210410055059.13518-2-sergio.paracuellos@gmail.comSigned-off-by: default avatarStephen Boyd <sboyd@kernel.org>
      48df7a26
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