- 25 Feb, 2020 21 commits
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Aric Cyr authored
Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Aric Cyr authored
[Why] When calculating nominal refresh rates, don't round. Only the VSIF needs to be rounded. [How] Revert rounding change for nominal and just round when forming the FreeSync VSIF. Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Peikang Zhang authored
[Why] Unused VMIDs were not evicted correctly [How] 1. evict_vmids() logic was fixed; 2. Added boundary check for add_ptb_to_table() and clear_entry_from_vmid_table() to avoid crash caused by array out of boundary; 3. For mod_vmid_get_for_ptb(), vimd is changed from unsigned to signed due to vimd is signed. Signed-off-by:
Peikang Zhang <peikang.zhang@amd.com> Reviewed-by:
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Samson Tam authored
[Why] Add optimization to allow pstate change support when all displays are off in DCN2. [How] Add clk_mgr_helper_get_active_plane_cnt() to sum plane_count for all valid stream_status[]. If plane_count is 0, then there are no active or virtual streams present. Use plane_count == 0 as extra condition to enable p_state_change_support in dcn2_update_clocks(). Signed-off-by:
Samson Tam <Samson.Tam@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Roman Li authored
[Why] We need DMCU for features like PSR and ABM. [How] Add path to dmcu firmware binary and load it for Navi12. Signed-off-by:
Roman Li <roman.li@amd.com> Reviewed-by:
Hersen Wu <hersenxs.wu@amd.com> Acked-by:
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Nicholas Kazlauskas authored
[Why] If we're doing backdoor load then do it entirely ourselves without invoking any of the frontdoor path to avoid potential issues with outdated tOS. [How] Check the load type and don't pass it to base if we don't want it loaded. Signed-off-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by:
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Nicholas Kazlauskas authored
[Why] When we execute the first command for ASIC_INIT for command table offloading we can hit a timing scenario such that the interrupts for the inbox wptr haven't been enabled yet and the first command is ignored until the second command is sent. [How] This happens when either the SCRATCH0 is already the correct status code or autoload check is unsupported. Clear SCRATCH0 during reset. Also ensure that we don't accidentally reset the ASIC again in case of a hang by clearing GPINT while we're at it. Signed-off-by:
Chris Park <Chris.Park@amd.com> Acked-by:
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Alvin Lee authored
[Why] According to HW team, PG is dropped for NV12, but programming the registers will still cause power to be consumed, so don't program for NV12. [How] Set function pointer to NULL if NV12 Signed-off-by:
Alvin Lee <alvin.lee2@amd.com> Reviewed-by:
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Hersen Wu authored
Signed-off-by:
Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com> Reviewed-by:
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Hersen Wu authored
Signed-off-by:
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Alvin Lee authored
[Why] Bugs occur when TX interrupt comes in when no USB-C on board. [How] Check PHY for USB-C before enabling TX interrupt in DMCU FW. Signed-off-by:
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Dmytro Laktyushkin authored
Currently there is a minor error in scaling filter coefficients caused by truncation to fit the HW registers.This error accummulates with increased taps, but has gone unnoticed due to vast majority of scaling being done with only 4 taps. Scaling filters are now updated using HW team's filter generator which has quantization error minimization built in. Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
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Aric Cyr authored
[Why] Since the i2c payload allocation can fail need to check return codes [How] Clean up i2c payload allocations and check for errors Signed-off-by:
Joshua Aberback <Joshua.Aberback@amd.com> Acked-by:
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Zhan Liu authored
[Why] core_link_read_dpcd() will invoke dm_helpers_dp_read_dpcd(), which needs to read dpcd info with the help of aconnector. If aconnector (dc->links[i]->prev) is NULL, then dpcd status cannot be read. As a result, dpcd read fails and a line of error will be printed out in dmesg.log as: "*ERROR* Failed to found connector for link!" [How] Make sure that aconnector (dc->links[i]->prev) is not NULL, then read dpcd status. Signed-off-by:
Zhan Liu <zhan.liu@amd.com> Reviewed-by:
Joseph Gravenor <Joseph.Gravenor@amd.com> Signed-off-by:
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Felix Kuehling authored
Using a heavy-weight TLB flush once is not sufficient. Concurrent memory accesses in the same TLB cache line can re-populate TLB entries from stale texture cache (TC) entries while the heavy-weight TLB flush is in progress. To fix this race condition, perform another TLB flush after the heavy-weight one, when TC is known to be clean. Move the workaround into the low-level TLB flushing functions. This way they apply to amdgpu as well, and KIQ-based TLB flush only needs to synchronize once. Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
shaoyun liu <shaoyun.liu@amd.com> Signed-off-by:
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Monk Liu authored
for bare-metal we alawys need to load sys/sos/kdb Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Shirish S authored
fixes S3 issue with IOMMU + S/G enabled @ 64M VRAM. Suggested-by:
Shirish S <shirish.s@amd.com> Reviewed-by:
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Alex Deucher authored
Make the IP block base output debug only. Reviewed-by:
Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by:
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Monk Liu authored
what: some os preemption path is messed up with world switch preemption fix: cleanup those logics so os preemption not mixed with world switch this patch is a general fix for issues comes from SRIOV MCBP, but there is still UMD side issues not resovlved yet, so this patch cannot fix all world switch bug. Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Monk Liu authored
fix system memory leak v2: fix coding style Signed-off-by:
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Monk Liu authored
1) we shouldn't load PSP kdb and sys/sos for VF, they are supposed to be handled by hypervisor 2) ih reroute doesn't work on VF thus we should avoid calling it, besides VF should not use those PSP register sets for PF 3) shouldn't load SMU ucode under SRIOV, otherwise PSP would report error Signed-off-by:
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- 19 Feb, 2020 5 commits
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Evan Quan authored
As the firmware versions of arcturus are different from other gfx9 ASICs. And the warning("CP firmware version too old, please update!") caused by this check can be eliminated. Signed-off-by: -
changzhu authored
The rlc version of raven_kicer_rlc is different from the legacy rlc version of raven_rlc. So it needs to add a judgement function for raven_kicer_rlc and avoid disable GFXOFF when loading raven_kicer_rlc. Signed-off-by:
changzhu <Changfeng.Zhu@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
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Guchun Chen authored
When NBIO's RAS error happens, before trigging GPU reset, it's needed to record error counter information, which can correct the error counter value missed issue when reading from debugfs. Signed-off-by:
Guchun Chen <guchun.chen@amd.com> Reviewed-by:
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Guchun Chen authored
Once sync flood interrupt is triggered by RAS error, before actual GPU recovery job, it's necessary to log on and print non-zero error counter, this will help user knows where the RAS error source is from quickly. Signed-off-by:
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Nathan Chancellor authored
Clang warns: ../drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link.c:980:36: warning: address of 'sink->edid_caps.panel_patch.skip_scdc_overwrite' will always evaluate to 'true' [-Wpointer-bool-conversion] if (&sink->edid_caps.panel_patch.skip_scdc_overwrite) ~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~ 1 warning generated. This is probably not what was intended so remove the address of operator, which matches how skip_scdc_overwrite is handled in the rest of the driver. While we're here, drop an extra newline after this if block. Fixes: a760fc1b ("drm/amd/display: add monitor patch to disable SCDC read/write") Link: https://github.com/ClangBuiltLinux/linux/issues/879Signed-off-by:Nathan Chancellor <natechancellor@gmail.com> Signed-off-by:
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- 13 Feb, 2020 1 commit
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Evan Quan authored
Since 'smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)' will always return false considering the 'smu_system_features_control(smu, false)' disabled all SMU features. Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Signed-off-by:
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- 12 Feb, 2020 13 commits
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Dan Carpenter authored
The copy_to_user() function returns the number of bytes remaining to be copied, but we want to return a negative error code to the user. Fixes: 030d5b97 ("drm/amdgpu: use amdgpu_device_vram_access in amdgpu_ttm_vram_read") Reviewed-by:
Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
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Alex Deucher authored
Otherwise we readback all ones. Fixes rlc counter readback while gfxoff is active. Reviewed-by:
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Alex Deucher authored
Otherwise we readback all ones. Fixes rlc counter readback while gfxoff is active. Reviewed-by:
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Alex Deucher authored
It's 25 Mhz (refclk / 4). This fixes the interpretation of the rlc clock counter. Acked-by:
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Alex Deucher authored
It's used by more than just DCN2.0. Fixes missing symbol when amdgpu is built without DCN support. Reviewed-by:
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Alex Deucher authored
to cover dcn2.x related headers. Reviewed-by:
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Alex Deucher authored
To cover DCN 2.x. Reviewed-by:
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Kent Russell authored
In certain situations the message could be reported dozens-to-hundreds of times, based on how often the function is called. E.g. If MCLK DPM, any calls to get/set MCLK will result in a failure message, potentially flooding dmesg. Ratelimit the warnings to avoid this flood. Signed-off-by:
Kent Russell <kent.russell@amd.com> Reviewed-by:
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Evan Quan authored
Otherwise, the cached dpm features status may be inconsistent under some case(e.g. baco reset of Navi asic). Signed-off-by:
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Bhawanpreet Lakha authored
there was a type in the terminate command. We should be calling psp_dtm_unload() instead of psp_hdcp_unload() Fixes: 143f2305 ("drm/amdgpu: psp DTM init") Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by:
Feifei Xu <Feifei.Xu@amd.com> Signed-off-by:
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Bhawanpreet Lakha authored
-msg_in is not needed for enabling encryption. -Use hdcp2_set_encryption instead of hdcp1_enable_encryption for hdcp2.2 Signed-off-by:
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Bhawanpreet Lakha authored
We were using incorrect byte order after we started using the drm_defines So fix it. Fixes: 02837a91 ("drm/amd/display: add and use defines from drm_hdcp.h") Signed-off-by:
JinZe.Xu <JinZe.Xu@amd.com> Signed-off-by:
Wenjing Liu <Wenjing.Liu@amd.com> Signed-off-by:
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Wenjing Liu authored
[why] HDCP DTM needs to be aware of the upto date display topology information in order to validate hardware consistency. [how] update HDCP DTM on update_stream_config call. Signed-off-by:
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